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March 2002 Release
389
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Integer Instructions
R
Integer Instructions
Integer instructions operate on the contents of GPRs. They use the GPRs (and sometimes
immediate values coded in the instruction) as source operands. Results are written into
GPRs. These instructions do not operate on memory locations. Integer instructions treat
the source operands as signed integers unless the instruction is explicitly identified as
performing an unsigned operation. For example, the
multiply high-word unsigned
(
mulhwu
)
and
divide-word unsigned
(
divwu
) instructions interpret both operands as unsigned
integers.
The following types of integer instructions are supported by the PowerPC architecture:
•
Arithmetic Instructions
•
Logical Instructions
•
Compare Instructions
•
Rotate Instructions
•
Shift Instructions
The arithmetic, shift, and rotate instructions can update and/or read bits from the XER.
Those instructions, plus the integer-logical instructions, can also update bits in the CR.
Unless otherwise noted, when XER and/or CR are updated, they reflect the value written
Figure 3-22:
Load and Store String Instructions
EA
Byte 1
Byte n-2
. . .
Byte 0
Byte n-1
EA + (n-1)
UG011_06_033101
Load String Example
0
7
Memory
GPRs
31
24
0
8
16
r
D
Byte 1
Byte 2
Byte 3
Byte 0
. . .
. . .
. . .
. . .
Byte n-1
0000_0000
0000_0000
Byte n-2
r
31
r
0
Store String Example
0
7
Memory
GPRs
31
24
0
8
16
r
D
Byte 1
Byte 2
Byte 3
Byte 0
. . .
. . .
. . .
. . .
Byte n-1
Byte n-2
r
31
r
0
Byte 1
Byte n-2
. . .
Byte 0
EA
Byte n-1
EA + (n-1)