March 2002 Release
663
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Alphabetical Instruction Listing
R
macchw
Multiply Accumulate Cross Halfword to Word Modulo Signed
Description
The low-order halfword of
r
A is multiplied by the high-order halfword of
r
B. The signed
product is added to the contents of
r
D and the sum is stored as a 33-bit temporary result.
The contents of
r
D are replaced by the low-order 32 bits of the temporary result. An
example of this operation is shown in
.
Pseudocode
prod
0:31
←
(
r
A)
16:31
×
(
r
B)
0:15
signed
temp
0:32
←
prod
0:31
+ (
r
D)
(
r
D)
←
temp
1:32
Registers Altered
•
r
D.
•
CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
•
XER[SO, OV] if OE
=
1.
Exceptions
•
None.
Compatibility
This instruction is implementation specific and is not guaranteed to be supported by other
PowerPC processors.
macchw
r
D,
r
A,
r
B
(OE=0, Rc=0)
macchw.
r
D,
r
A,
r
B
(OE=0, Rc=1)
macchwo
r
D,
r
A,
r
B
(OE=1, Rc=0)
macchwo.
r
D,
r
A,
r
B
(OE=1, Rc=1)
XO Instruction Form
4
r
D
r
A
r
B
OE
172
Rc
0
6
1
1
1
6
2
1
2
2
3
1
