Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 653
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
lswi
Load String Word Immediate
Description
An effective address (EA) is determined by the r A field as follows:
• If the r A field is 0, the EA is 0.
• If the r A field is not 0, the contents of register r A are used as the EA.
Let n specify the byte count. If the NB field is 0, n is 32. Otherwise, n is equal to NB.
Let nr specify the number of registers to load with data. nr
=
CEIL( n
÷
4).
Let R
FINAL
specify the last register to be loaded with data. n consecutive bytes starting at
the memory address referenced by EA are loaded into GPRs r D through R
FINAL
. The
sequence of registers wraps around to r 0 if necessary. R
FINAL
=
r D
+
nr
−
1 (modulo 32).
Bytes are loaded in each register starting with the most-significant register byte and ending
with the least-significant register byte. If the byte count is exhausted before R
FINAL
is filled,
the remaining bytes in R
FINAL
are loaded with 0.
Pseudocode
EA
←
(
r A|0)
if NB
=
0
then n
←
32
else n
←
NB
R
FINAL
←
((
r D + CEIL(n/4)
−
1) % 32)
reg
←
r D
−
1
bit
←
0
do while n > 0
if bit
=
0
then
reg
←
reg + 1
if reg
=
32
then reg
←
0
if ((reg
≠
r A)
∨
(reg
=
R
FINAL
))
then (GPR(reg))
←
0
if ((reg
≠
r A)
∨
(reg
=
R
FINAL
))
then (GPR(reg)
bit:bit+7
)
←
MS(EA,1)
bit
←
bit + 8
if bit
=
32
then bit
←
0
EA
←
EA + 1
n
←
n
−
1
lswi r D, r A, NB
X Instruction Form
31 r D r A NB 597 0
0 6 1
1 1
6 2
1 3
1