Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 651
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
lmw
Load Multiple Word
Description
An effective address (EA) is calculated by adding a displacement to a base address, which
are formed as follows:
• The displacement is formed by sign-extending the 16-bit d instruction field to 32 bits.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
Let n
=
32
−
r D.
n consecutive words starting at the memory address referenced by EA are loaded into
GPRs r D through r 31.
Pseudocode
EA
←
( r A|0) + EXTS(d)
n
←
r D
do while n
≤
31
if ((n
≠
r A)
∨
(n
=
31))
then (GPR(n))
←
MS(EA,4)
n
←
n + 1
EA
←
EA + 4
Registers Altered
• r D through r 31.
Exceptions
• Data storage—if the access is prevented by no-access-allowed zone protection. This
only applies to accesses in user mode when data relocation is enabled.
• Data TLB miss—if data relocation is enabled and a valid translation-entry
corresponding to the EA is not found in the TLB.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• r A is in the range of registers to be loaded, including the case r A
=
r D
=
0. The word that
would have been loaded into r A is discarded.
lmw r D, d( r A)
D Instruction Form
46 r D r A d
0 6 1
1 1
6 3
1