Xilinx Virtex-II Pro PPC405, User Manual

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Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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Chapter 2
Operational Concepts
This chapter describes the operational concepts governing the PPC405 programming
model. These concepts include the execution and memory-access models, processor
operating modes, memory organization and management, and instruction conventions.
Execution Model
From a software viewpoint, PowerPC
®
processors implement a sequential-execution model .
That is, the processors appear to execute instructions in program order. Internally and
invisible to software, PowerPC processors can execute instructions out-of-order and can
speculatively execute instructions. The processor is responsible for maintaining an in-
order execution state visible to software. The execution of an instruction sequence can be
interrupted by an exception caused by one of the executing instructions or by an
asynchronous event. The PPC405
does not support out-of-order instruction execution.
However, the processor does support speculative instruction execution, typically by
predicting the outcome of branch instructions.
As described in Ordering Memory Accesses , page 448 , the PowerPC architecture specifies
a weakly consistent memory model for shared-memory multiprocessor systems. The
weakly consistent memory model allows system bus operations to be reordered
dynamically. The goal of reordering bus operations is to reduce the effect of memory
latency and improving overall performance. In single-processor systems, loads and stores
can be reordered dynamically to allow efficient utilization of the processor bus. Loads can
be performed speculatively to enhance the speculative-execution capabilities. This model
provides an opportunity for significantly improved performance over a model that has
stronger memory-consistency rules, but places the responsibility for access ordering on the
programmer.
When a program requires strict instruction-execution ordering or memory-access ordering
for proper execution, the programmer must insert the appropriate ordering or
synchronization instructions into the program. These instructions are described in
Synchronizing Instructions , page 424 . The concept of synchronization is described in the
Synchronization Operations section that follows.
The PPC405 supports many aspects of the weakly consistent model but not all of them.
Specifically, the PPC405
does not provide hardware support for multiprocessor memory
coherency and does not support speculative loads. If the order of memory accesses is
important to the correct operation of a program, care must be taken in porting such a
program from the PPC405 to a processor that supports multiprocessor memory coherency
and speculative loads.