Xilinx Virtex-II Pro PPC405, User Manual

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582 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
andc
AND with Complement
Description
The contents of register r S are ANDed with the one’s complement of the contents of
register r B and the result is loaded into register r A.
Pseudocode
( r A)
←
( r S)
∧ ¬
( r B)
Registers Altered
• r A.
• CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
Exceptions
• None.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
andc r A, r S , r B (Rc=0)
andc. r A,
r S
, r B (Rc=1)
X Instruction Form
31 r S r A r B 60 Rc
0 6 1
1 1
6 2
1 2 3
1