Xilinx Virtex-II Pro PPC405, User Manual

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580 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 11: Instruction Set
R
addze
Add to Zero Extended
Description
The sum of the contents of register r A and XER[CA] is loaded into register r D. XER[CA] is
updated to reflect the unsigned magnitude of the resulting sum.
The add-extended instructions can be used to perform addition on integers larger than 32
bits, as described on
page 390 .
Pseudocode
( r D)
←
( r A) + XER[CA]
if (
r D)
2
32
−
1
then XER[CA]
←
1
else XER[CA]
←
0
Registers Altered
• r D.
• XER[CA].
• CR[CR0]
LT, GT, EQ, SO
if Rc
=
1.
• XER[SO, OV] if OE
=
1.
Exceptions
• None.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
• Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the PowerPC user instruction-set architecture (UISA). It is
implemented by all PowerPC processors.
addze r D, r A (OE=0, Rc=0)
addze. r D, r A (OE=0, Rc=1)
addzeo r D, r A (OE=1, Rc=0)
addzeo. r D, r A (OE=1, Rc=1)
XO Instruction Form
31 r D r A 0 0 0 0 0 OE 202 Rc
0 6 1
1 1
6 2
1 2
2 3
1
>
u