532
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 8:
Timer Resources
R
This method uses the watchdog interrupt. The watchdog interrupt handler clears
TSR[WIS]
=
0 before returning. TSR[ENW] is never cleared and is always set to 1. If an
error prevents watchdog interrupts, consecutive watchdog time-outs force a reset.
•
Method (2)—the combination of a system-service routine and an interrupt handler
manages the state machine.
This method attempts to avoid watchdog interrupts. Here, a system-service routine
periodically clears the TSR[ENW] bit to 0, preventing watchdog interrupts. The system
service routine must run more frequently than the watchdog time-out period. The
fixed-interval timer can be used to initiate this routine at the proper time interval.
If an error prevents the system-service routine from clearing TSR[ENW], the next
watchdog time-out causes a watchdog interrupt. The interrupt handler can attempt to
correct the problem and clear both TSR[ENW] and TSR[WIS]. If an error prevents
watchdog interrupts, another watchdog time-out forces a reset.
•
Method (3)—a system-service routine manages the state machine.
This method avoids the watchdog interrupt entirely and requires that the interrupt be
disabled. A system-service routine periodically clears the TSR[WIS] bit to 0 and leaves
TSR[ENW] set to 1. If an error prevents the system-service routine from clearing
TSR[WIS], the next watchdog time-out causes a reset. As with method (2), the system
service routine must run more frequently than the watchdog time-out period. The
fixed-interval timer can be used to initiate this routine at the proper time interval.
Disabling Watchdog Time-outs
After a reset (including power-on reset), watchdog interrupts are disabled because
MSR[CE]
=
0. However, watchdog time-outs continue to occur because the time-base
register is always incrementing, and a valid watchdog interval is always specified by
TCR[WP].
Unless prevented by software, consecutive watchdog time-outs cause the state machine to
enter the “Reset” state shown in
. If the state machine enters the “Reset” state
and TCR[WRC]
=
00 (the value following a reset), watchdog time-outs become silent,
causing neither an interrupt or reset. This effectively disables the event.
Programmable-Interval Timer Events
The programmable-interval timer (PIT) is a 32-bit decrementing register that is clocked at
the same frequency as the time-base register. The PIT begins decrementing when it is
loaded with a non-zero value and it stops decrementing when the contents reach 0. When
the PIT contains a value of 1 and is decremented, a PIT event occurs. The value in the PIT
following a PIT event depends on whether auto-reload mode is enabled:
•
If auto-reload is not enabled (TCR[ARE]
=
0), the next PIT value is 0 and decrementing
is halted. Loading the PIT with a value of 0 does not cause a PIT event.
•
If auto-reload is enabled (TCR[ARE]
=
1), the PIT is loaded with the last value written
to it. Decrementing continues from that value.
A PIT event causes a PIT interrupt when
both
of the following bits are set to 1:
•
The PIT interrupt-enable bit in the timer-control register, TCR[PIE].
•
The external-enable bit in the machine-state register, MSR[EE].
PIT events always set the PIT-interrupt status bit in the timer-status register (TSR[PIS]
=
1).
This happens whether or not PIT interrupts are enabled. If TSR[PIS]
=
1 and the PIT
interrupt is disabled, the PIT interrupt is pending. A PIT interrupt occurs if the status bit is
set and the interrupt is enabled.
PIT events are disabled as follows:
•
Disable PIT interrupts by clearing TCR[PIE]
=
0.
•
Clear TSR[PIS] to 0 to remove pending PIT interrupts.
