Xilinx Virtex-II Pro PPC405, User Manual

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518 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 7: Exceptions and Interrupts
R
Watchdog-Timer Interrupt (0x1020)
Interrupt Classification
• Critical—return using the rfci instruction.
• Asynchronous.
• Precise.
Description
A watchdog-timer exception is caused by a time-out on the watchdog timer. For a
watchdog-timer interrupt to occur, the interrupt must be enabled and the processor must
be enabled to detect the watchdog-timer exception, as follows:
• The watchdog-timer interrupt is enabled only by setting both of the following:
-
The watchdog-interrupt enable bit in the timer-control register (TCR[WIE]) must
be set to 1.
- The critical-interrupt enable bit in the machine-state register (MSR[CE]) must be
set to 1.
If either TCR[WIE]
=
0 or MSR[CE]
=
0, a watchdog-timer interrupt does not occur.
• The processor detects a watchdog-timer exception when:
-
The enable-next-watchdog bit in the timer-status register (TSR[ENW]) is set to 1.
- The watchdog-interrupt status bit in the timer-status register (TSR[WIS]) is
cleared to 0.
- A 0 to 1 transition occurs on the time-base bit corresponding to the watchdog time
period.
During the cycle following detection of the watchdog time-out, the processor sets
TSR[WIS] to 1. At the beginning of the
next cycle, the processor detects TSR[WIS]
=
1 and
causes the watchdog-timer interrupt to occur.
This exception is persistent, but the persistence prevents further interrupts from occurring.
This function causes an interrupt to occur on the first watchdog time-out, but prevents
interrupts on subsequent time-outs. To enable additional interrupts, the interrupt handler
must clear the exception status in TSR[WIS] before returning.
See Chapter 8, Watchdog-Timer Events , for more information on the watchdog timer and
its relationship to the TCR and TSR.
Affected Registers
Register Value After Interrupt
SRR0 Not used.
SRR1
SRR2 Loaded with the effective address of the next-sequential instruction to be
executed at the point the interrupt occurs.
SRR3 Loaded with a copy of the MSR at the point the interrupt occurs.
ESR Not used.
DEAR
MSR [AP, APE, WE, CE, EE, PR, FP, FE0, DWE, DE, FE1, IR, DR]
←
0.
[ME]
←
Unchanged.