Xilinx Virtex-II Pro PPC405, User Manual

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March 2002 Release www.xilinx.com 481
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Translation Look-Aside Buffer
R
The following sections describe the conditions under which exceptions occur due to TLB-
access failures.
Data-Storage Exception
When data-address translation is enabled (MSR[DR]
=
1), a data-storage exception occurs
when access to a page is not permitted for any of the following reasons:
• From user mode:
-
The TLB entry specifies a zone field that prevents access to the page
(ZPR[Z
n ]
=
00). This applies to load, store, dcbf , dcbst , dcbz , and icbi instructions.
- The TLB entry specifies a read-only page (TLBLO[WR]
=
0) that is not otherwise
overridden by the zone field (ZPR[Z n ]
≠
11). This applies to store and dcbz
instructions.
- The TLB entry specifies a U0 page (TLBHI[U0]
=
1) and U0 exceptions are enabled
(CCR0[U0XE]
=
1). This applies to store and dcbz instructions.
• From privileged mode:
-
The TLB entry specifies a read-only page (TLBLO[WR]
=
0) that is not otherwise
overridden by the zone field (ZPR[Z n ]
≠
10 and ZPR[Z n ]
≠
11). This applies to
store, dcbi , dcbz , and dccci instructions.
- The TLB entry specifies a U0 page (TLBHI[U0]
=
1) and U0 exceptions are enabled
(CCR0[U0XE]
=
1). This applies to store, dcbi , dcbz , and dccci instructions.
See Data-Storage Interrupt (0x0300) , page 506 , for more information on this exception and
Zone Protection , page 482 , for more information on zone protection.
Instruction-Storage Exception
When instruction-address translation is enabled (MSR[IR]
=
1), an instruction-storage
exception occurs when access to a page is not permitted for any of the following reasons:
• From user mode:
-
The TLB entry specifies a zone field that prevents access to the page
(ZPR[Z
n ]
=
00).
- The TLB entry specifies a non-executable page (TLBLO[EX]
=
0) that is not
otherwise overridden by the zone field (ZPR[Z n ]
≠
11).
- The TLB entry specifies a guarded-storage page (TLBLO[G]=1).
• From privileged mode:
-
The TLB entry specifies a non-executable page (TLBLO[EX]
=
0) that is not
otherwise overridden by the zone field (ZPR[Z n ]
≠
10 and ZPR[Z n ]
≠
11).
- The TLB entry specifies a guarded-storage page (TLBLO[G]=1).
See Instruction-Storage Interrupt (0x0400) , page 508 , for more information on this
exception, Guarded (G) , page 452 , for more information on guarded storage, and Zone
Protection , page 482 , for more information on zone protection.
Data TLB-Miss Exception
When data-address translation is enabled (MSR[DR]
=
1), a data TLB-miss exception occurs
if a valid, matching TLB entry was not found in the TLB (shadow and UTLB). Any load,
store, or cache instruction (excluding cache-touch instructions) can cause a data TLB-miss
exception. See
Data TLB-Miss Interrupt (0x1100) , page 519 , for more information.
Instruction TLB-Miss Exception
When instruction-address translation is enabled (MSR[IR]
=
1), an instruction TLB-miss
exception occurs if a valid, matching TLB entry was not found in the TLB (shadow and
UTLB). Any instruction fetch can cause an instruction TLB-miss exception. See
Instruction
TLB-Miss Interrupt (0x1200) , page 520 , for more information.