Xilinx Virtex-II Pro PPC405, User Manual

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410 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
Multiply-Accumulate Low-Halfword to Word Instructions
Table 3-42 shows the PPC405 multiply-accumulate low-halfword to word instructions. These
instructions multiply the low halfword of both source operands, r A[16:31] and r B[16:31],
producing a 32-bit product. The product is signed or unsigned, depending on the
instruction. This product is added to the value in the destination register,
r D, producing a
33-bit intermediate result. Generally, r D is loaded with the lower-32 bits of the 33-bit
intermediate result. However, if the instruction performs saturating arithmetic and the
intermediate result overflows,
r D is loaded with the nearest representable value (see
Modulo and Saturating Arithmetic , page 405 ).
For each type of instruction shown in Table 3-42 , the “Operation” column indicates the
multiply-accumulate operation performed. The column also shows, on an instruction-by-
instruction basis, how the XER and CR registers are updated (if at all).
Figure 3-29: Multiply-Accumulate High-Halfword to Word Operation
UG011_21_033101
r D
0 31
0 32
r A
0 31 16
r B
0 31 15
×
r D
0 31
+
Intermediate Result
1