Virtex-4 ML455 PCI/PCI-X Board
37
UG084 (v1.0) May 17, 2005
JTAG Port
R
Figure 4-3:
JTAG Cable Hook-up
Figure 4-4:
Photo of ML455 Board and PC IV Pod Flat Cable Connection to P5
Table 4-2:
P5 JTAG Header Signal Descriptions and Pin Assignments
Signal
Name
Description
P5 Pin
Number
FPGA Pin
Number
CPLD Pin
Number
Flash Pin
Number
JTAG_TMS
JTAG TMS to
FPGA/CPLD/
FLASH
4
Y11
10
E2
JTAG_TCK
JTAG TCK to
FPGA/CPLD/
FLASH
6
W12
11
H3
JTAG_TDO
JTAG TDO
from FLASH
8
N/A
N/A
E6
JTAG_TDI
JTAG TDI to
FPGA TDI
10
Y12
N/A
N/A
P5
JTAG
Connector
1
3
5
7
9
11
13
2
4
6
8
10
12
14
3.3V
2 mm
TCK
TDO
TDI
TMS
UG084_c4_03_050705
www.BDTIC.com/XILINX
