Appendix D
Using the High Speed Debug Port
Over PCIe for Design Debug
The high speed debug port (HSDP) allows the Vivado Design Suite to connect to the FPGA
debug cores through non-JTAG interfaces. The standard Vivado Design Suite debug feature uses
JTAG to connect to the hardware FPGA resources and performs debug through Vivado. This
appendix focuses on using PCIe to perform debug over a PCIe link rather than the standard JTAG
debug interface. This is referred to as HSDP-over-PCIe and allows for Vivado ILA waveform
capture, VIO debug control, and interaction with other Xilinx debug cores using the PCIe link as
the communication channel.
HSDP-over-PCIe should be used to perform FPGA debug remotely using the Vivado Design Suite
debug feature when JTAG debug is not available. This is commonly used for data center
applications where the FPGA is connected to a PCIe host system without any other connections
to the hardware device.
Using debug over PCIe requires software, driver, and FPGA hardware design components.
Because there is an FPGA hardware design component to HSDP-over-PCIe debug, you cannot
perform debug until the FPGA is already loaded with a FPGA hardware design that implements
HSDP-over-PCIe and PCIe link to the host PC is established. This is achieved by loading an
HSDP-over-PCIe enabled design into the configuration flash on the board prior to inserting the
card into the data center location. Because debug using HSDP-over-PCIe is dependent on the
PCIe communication channel, this should not be used to debug PCIe link related issues.
Overview
The Versal
®
ACAP has an integrated debug that resides in the PMC. The integrated debug
subsystem includes the test access port (TAP) controller, the Arm
®
debug access port (DAP)
controller, and the debug packet controller (DPC). The DPC receives command packets, referred
to as debug and trace packets (DTP), from one or more debug host interfaces, then generates
reply packets and transmits them back to the debug host. The Versal ACAP has four debug host
interfaces that are connected to the DPC for interaction with external debug hosts.
• Serial, low-speed JTAG interface attached to the debug access port (DAP) controller
• Serial, high-speed debug port (HSDP) connected to the Aurora protocol unit
Appendix D: Using the High Speed Debug Port Over PCIe for Design Debug
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