Appendix B
GT Selection and Pin Planning for
CPM5
CAUTION! The guidance provided in this appendix contains preliminary information and is subject to
change without notice.
This appendix provides guidance on gigabit transceiver (GTYP) selection for CPM5 and key
recommendations to be considered during pin planning. For each PCIe interface, these include:
• GTYP quad placement
• REFCLK placement
• RESET placement
CPM5 has dedicated connectivity to a specific set of four GTYP quads which are adjacent to
each other, and adjacent to CPM5. If unused by CPM5, certain quads may be available for use
with the high-speed debug port (HSDP), but no quad can be bypassed to the programmable logic.
The remaining GT in the device are available for other use cases, if the GT of interest provide the
necessary protocol support as required for the desired use cases.
Through the GTYP quads with dedicated connectivity to the CPM5, specific REFCLK inputs must
be used to provide a reference clock to GTYP quads, which internally provide derived clocks to
the CPM5. In the common case of add-in-card designs, the reference clock is sourced from the
edge connector. In other cases, such as system-board designs, embedded designs, and cabled
interconnect, a local oscillator is typically required.
RECOMMENDED: Although the CPM5 can support a variety of reference clock frequencies, Xilinx
strongly recommends that designers selecting local oscillators use a 100 MHz reference clock as described
in the PCI Express Card Electromechanical Specification unless there is a compelling reason to use a
different supported frequency.
As part of the Versal
®
architecture integrated shell, specific reset inputs must be used to provide
a reset to the GTYP and the CPM5. In the common case of add-in-card designs, the reset is
sourced from the edge connector. In the case of a system-board or embedded design, the system
is responsible for generating reset signals and sourcing them to devices as required for the
desired use case. Where cabled interconnect is used, consult the cable specification for
information about if, and how, it accommodates sideband signaling for reset.
The remainder of this appendix is divided into these sections:
Appendix B: GT Selection and Pin Planning for CPM5
PG346 (v3.3) November 16, 2022
CPM Mode for PCI Express
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