VC7203 GTX Transceiver Characterization Board
41
UG957 (v1.0) October 10, 2012
Detailed Description
XADC
Callout
7 Series FPGAs provide an Analog Front End (XADC) block. The XADC block includes a
dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors.See
, 7 Series
FPGAs XADC User Guide
for details on the capabilities of the analog front
end.
The VC7203 board provides two options for providing power (VCCADC) to the analog
circuitry in the XADC. Either option can be selected by placing a shunt in one of two
positions on the 3-pin VCCADC SELECT header, J141 (callout
,
):
•
Pins 1-2 (VCCAUX):
In this configuration VCCADC is provided from VCCAUX
through a low pass filter network.
•
Pin 2-3 (REG):
In this configuration VCCADC is provided by an on-board regulator,
U43 (Analog Devices P/N ADP123AUJZ-R7). The output voltage of the regulator
VCCADC can be adjusted using the potentiometer R233.
In addition, the VC7203 board provides two options for providing the reference voltage for
the analog-to-digital converter. Either option can be selected by placing a shunt in one of
two positions on the 3-pin VREF SEL header J142 (callout
,
•
Pins 1-2 (REG):
In this configuration the ADC reference voltage is provided by an
on-board, low-temperature coefficient 1.25V reference, U45 (Texas Instruments P/N
REF3012AIDBZT)
•
Pin 2-3 (AGND):
In this configuration the VREFP on XADC is connected to analog
ground and the ADC uses an on-chip reference.
I
2
C Bus Management
The I
2
C bus is controlled through U39, an 8-channel I
2
C-bus multiplexer (NXP
Semiconductor PCA9547). The FPGA communicates with the multiplexer through I
2
C
data and clock signals mapped to FPGA pins E21 and F21, respectively. The I
2
C idcode for
the PCA9547 device is
0x70
. The bus hosts four components:
•
SuperClock-2 module
•
7 Series GTX transceiver power supply module
AT19
FMC3_LA30_N
H35
AV16
FMC3_LA31_P
G33
AW16
FMC3_LA31_N
G34
AT16
FMC3_LA32_P
H37
AU16
FMC3_LA32_N
H38
BB19
FMC3_LA33_P
G36
BB18
FMC3_LA33_N
G37
AR20
FMC3_PRSNT_M2C_L
H2
Table 1-20:
VITA 57.1 FMC1 HPC Connections at JA4
(Cont’d)
U1 FPGA Pin
Net Name
FMC Pin
