Xilinx VC707, User Manual

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VC707 Evaluation Board www.xilinx.com 15
UG885 (v1.2) February 1, 2013
Feature Descriptions
The VC707 DDR3 SODIMM interface adheres to the constraints guidelines in the DDR3
Design Guidelines section of UG586 , 7 Series FPGAs Memory Interface Solutions User Guide .
The VC707 DDR3 SODIMM interface is a 40
Ω
impedance implementation. Other memory
interface details are available in UG586 and UG473 , 7 Series FPGAs Memory Resources
User Guide .
Linear BPI Flash Memory
[ Figure 1-2 , callout 3 ]
The Linear BPI Flash memory located at U3 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI Flash memory device is packaged in a 64-pin BGA.
• Part number: PC28F00AG18FE (Numonyx)
• Supply voltage: 1.8V
• Datapath width: 16 bits (26 address lines and 7 control signals)
• Data rate: Up to 40 MHz
The Linear BPI Flash memory can synchronously configure the FPGA in Master BPI mode
at the 40 MHz data rate supported by the PC28F00AG18FE flash memory by using a
configuration bitstream generated with bitgen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external
E28 DDR3_DQS7_N 186 DQS7_N
E27 DDR3_DQS7_P 188 DQS7_P
H20 DDR3_ODT0 116 ODT0
H18 DDR3_ODT1 120 ODT1
C29 DDR3_RESET_B 30 RESET_B
J17 DDR3_S0_B 114 S0_B
J20 DDR3_S1_B 121 S1_B
G17 DDR3_TEMP_EVENT 198 EVENT_B
F20 DDR3_WE_B 113 WE_B
K17 DDR3_CAS_B 115 CAS_B
E20 DDR3_RAS_B 110 RAS_B
K19 DDR3_CKE0 73 CKE0
J18 DDR3_CKE1 74 CKE1
G18 DDR3_CLK0_N 103 CK0_N
H19 DDR3_CLK0_P 101 CK0_P
F19 DDR3_CLK1_N 104 CK1_N
G19 DDR3_CLK1_P 102 CK1_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
FPGA (U1)
Pin
Net Name
J1 DDR3 Memory
Pin Number Pin Name