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ML628 Board User Guide
UG771 (v1.0.1) June 28, 2011
Chapter 1:
ML628 Board Features and Operation
four headers. The FPGA JTAG interface can also be driven directly from these headers by
attaching the flying wire JTAG cable to pin 2 of each header.
Figure 1-9
shows a more
detailed representation of the isolation jumpers as part of the broader JTAG chain in
Figure 1-8
.
Table 1-8
indicates the FPGA pin name associated with each jumper.
200 MHz 2.5V LVDS Oscillator
[
Figure 1-2
, callout
10
]
The ML628 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
Table 1-9
lists the FPGA pin connections to the LVDS oscillator.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1–3 and 2–4 (LVDS).
Single-Ended SMA Global Clock Inputs
[
Figure 1-2
, callout
11
]
The ML628 board provides two single-ended clock input SMA connectors that can be used
for connecting to an external function generator. The FPGA clock pins are connected to the
SMA connectors as shown in
Table 1-10
.
X-Ref Target - Figure 1-9
Figure 1-9:
JTAG Isolation Jumpers
Table 1-8:
JTAG Isolation Jumpers
Reference Designator
FPGA Pin Name
J22
TMS
J23
TDI
J195
TDO
J196
TCK
UG771_c1_09_022211
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
U25
TCK
TDO
TDI
TMS
FPGA
U1
J196
J195
J23
J22
Table 1-9:
LVDS Oscillator Global Clock Connections
FPGA Pin
Net Name
U7 Pin
AK13
IIO_LVDS_GC_34_P
4
AK12
IO_LVDS_GC_34_N
5