R
ML501 Evaluation Platform
User Guide
UG226 (v1.3) November 10, 2008
Page 1: ...R ML501 Evaluation Platform User Guide UG226 v1 3 November 10 2008...
Page 2: ...BILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY...
Page 3: ...Output With SMA Connectors 16 4 Oscillator Sockets 18 5 LCD Brightness and Contrast Adjustment 18 6 DIP Switches Active High 18 7 User and Error LEDs Active High 19 8 User Pushbuttons Active High 20...
Page 4: ...ation Address and Mode DIP Switches 32 32 Encryption Key Battery 32 33 SPI Flash 33 34 IIC Fan Controller and Temperature Voltage Monitor 33 35 Piezo 33 36 FMC Connectors for Power Supply Analysis 33...
Page 5: ...501 board Appendix B References Additional Documentation The following documents are also available for download at http www xilinx com virtex5 Virtex 5 FPGA Family Overview The features and product s...
Page 6: ...ncryption Boundary Scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces Virtex 5 FPGA System Monitor User Guide The System Monitor functionalit...
Page 7: ...t Convention Meaning or Use Example Blue text Cross reference link to a location in the current document See the section Additional Documentation for details Red text Cross reference link to a locatio...
Page 8: ...8 www xilinx com ML501 Evaluation Platform UG226 v1 3 November 10 2008 Preface About This Guide R...
Page 9: ...shbuttons Expansion header with 32 single ended I O 16 LVDS capable differential pairs 14 spare I Os shared with buttons and LEDs power JTAG chain expansion capability and IIC bus expansion Stereo AC9...
Page 10: ...nt version of this user guide in PDF format Example design files for demonstration of Virtex 5 FPGA features and technology Demonstration hardware and software configuration files for the System ACE c...
Page 11: ...ash Cfg Slave Serial JTAG JTAG JTAG JTAG Master Serial XGI Header USB Controller 10 100 1000 Ethernet PHY AC97 Audio CODEC Battery and Fan Header CF PC4 RS 232 XCVR Video DAC 16 X 32 Character LCD IIC...
Page 12: ...m board is shown in Figure 1 2 front and Figure 1 3 page 13 back The numbered sections on the pages following the figures contain details on each feature Figure 1 2 Detailed Description of Virtex 5 FP...
Page 13: ...Detailed Description R Note The label on the CompactFlash CF card shipped with your board might differ from the one shown Figure 1 3 Detailed Description of Virtex 5 FPGA ML501 Evaluation Platform Com...
Page 14: ...ectMAP Slave SelectMAP Byte wide Peripheral Interface BPI Up BPI Down and SPI modes See the Configuration Options page 36 section for more information I O Voltage Rails The FPGA has 14 banks The I O v...
Page 15: ...summarized in Table 1 2 Table 1 2 DCI Capability of FPGA Bank FPGA Bank DCI Capability 1 Not supported 2 Not supported 3 Not supported 4 Not supported 11 Yes 49 9 resistors are installed 12 Not suppo...
Page 16: ...engths for data signals to the corresponding data strobe signal as defined in the MIG user guide See Appendix B References for links to additional information about MIG and Virtex 5 FPGAs in general D...
Page 17: ...pair of SMA connectors This allows the FPGA to drive a precision clock to an external device such as a piece of test equipment Table 1 3 summarizes the differential SMA clock pin connections Table 1...
Page 18: ...change the factory default configuration of the clock generator chip the related reference design material might not work as designed Instructions for returning the IDT5V9885 to the factory default co...
Page 19: ...the LED signals to be used as higher performance I O by way of the XGI expansion connector Table 1 6 summarizes the LED definitions and connections GPIO_DIP_SW6 U5 GPIO_DIP_SW7 U7 GPIO_DIP_SW8 T7 Tabl...
Page 20: ...ferential FPGA I Os ground 2 5V 3 3V 5V power JTAG chain and the IIC bus All signals on connectors J4 and J6 have matched length traces that are matched to each other Differential Expansion I O Connec...
Page 21: ...5 8 6 HDR2_8 HDR2_6 E25 E26 12 10 HDR2_12 HDR2_10 G21 G22 16 14 HDR2_16 HDR2_14 P19 N19 20 18 HDR2_20 HDR2_18 J25 J26 24 22 HDR2_24 HDR2_22 R22 R23 28 26 HDR2_28 HDR2_26 N22 N21 32 30 HDR2_32 HDR2_30...
Page 22: ...o 2 5V or 3 3V by setting jumper J20 Table 1 10 summarizes the single ended connections on this expansion I O connector Table 1 10 Expansion I O Single Ended Connections J6 J6 Pin Schematic Net Name F...
Page 23: ...ended onto the expansion connector to allow additional IIC devices to be bused together If the expansion IIC bus is to be utilized the user must have the IIC pull up resistors present on the expansion...
Page 24: ...PGA_EXP_TMS Expansion TMS 12 FPGA_EXP_TCK Expansion TCK 13 FPGA_EXP_TDO Expansion TDO 14 FPGA_EXP_TDI Expansion TDI 15 GPIO_LED_N Y8 LED North 16 SW3 N A22 GPIO Switch North 17 GPIO_LED_C T22 LED Cent...
Page 25: ...ial port on a computer The serial port is designed to operate up to 115200 Bd An interface chip is used to shift the voltage level between FPGA and RS 232 signals Note The FPGA is connected only to th...
Page 26: ...pport an external video monitor The DVI circuitry utilizes a Chrontel CH7301C capable of 1600 X 1200 resolution with 24 bit color The video interface chip drives both the digital and analog signals to...
Page 27: ...em ACE CF project within the FAT16 partition However the root directory must not contain more than a total of 16 folder and or file entries including deleted entries When ejecting or unplugging the Co...
Page 28: ...organized as 256K x 36 bits This organization provides for a 32 bit data bus with support for four parity bits Note The SRAM and FLASH memory share the same data bus 19 Linear Flash Chips A NOR linea...
Page 29: ...B commands The firmware for this processor can be stored in its own dedicated IIC EEPROM U28 or can be downloaded from a host computer via a peripheral connector The USB controller s serial port is co...
Page 30: ...A debug The JTAG port supports the Xilinx Parallel Cable III Parallel Cable IV or Platform USB cable products Third party configuration products might also be available The JTAG chain can also be exte...
Page 31: ...The PWR Good LED lights when the 5V supply is applied 28 INIT LED The INIT LED lights upon power up to indicate that the FPGA has successfully powered up and completed its internal power on process 29...
Page 32: ...e VBATT pin of the FPGA to hold the encryption key for the FPGA Table 1 14 Configuration Address DIP Switch Settings Switch SW15 Function 1 Config Address 2 2 Config Address 1 3 Config Address 0 4 MOD...
Page 33: ...heatsink fan unit but can accommodate one for example Calgreg Electronics Smart CLIP family of heatsink fan assemblies 35 Piezo A piezo audio transducer is provided to allow simple beeps tones and so...
Page 34: ...es Access to external voltages is provided through a dedicated analog input pair VP VN and 16 user selectable analog inputs known as auxiliary analog inputs VAUXP 15 0 VAUXN 15 0 The System Monitor is...
Page 35: ...7_N VAUXP 7 E25 J4 8 HDR2_8_SM_7_P VAUXN 8 F25 J4 2 HDR2_2_SM_8_N VAUXP 8 F24 J4 4 HDR2_4_SM_8_P VAUXN 9 P20 J4 62 HDR2_62_SM_9_N VAUXP 9 P21 J4 64 HDR2_64_SM_9_P VAUXN 10 R23 J4 22 HDR2_22_SM_10_N VA...
Page 36: ...the JTAG chain allows a host computer to download bitstreams to the FPGA using the iMPACT software tool PC4 also allows debug tools such as the ChipScope Pro Analyzer or a software debugger to access...
Page 37: ...ng the FPGA The configuration mode DIP switches on the board must be set to match the programming method being used by the Platform Flash PROM When set correctly the Platform Flash PROM programs the F...
Page 38: ...38 www xilinx com ML501 Evaluation Platform UG226 v1 3 November 10 2008 Chapter 1 ML501 Evaluation Platform R...
Page 39: ...ngs using the following equipment Xilinx download cable JTAG flying wires Downloading to the ML50x Board 1 Connect a Xilinx download cable to the board using flying leads connected to jumper J3 Figure...
Page 40: ...rogramming the IDT Clock Chip R 7 To finish programming the chip cycle the power by turning off the board power switch 8 After turning the board back on verify that the clock frequencies are correct F...
Page 41: ...PGA Configuration User Guide 8 UG192 Virtex 5 FPGA System Monitor User Guide 9 UG195 Virtex 5 FPGA Packaging and Pinout Specification Documents specific to the ML501 Evaluation Platform 10 UG228 ML501...
