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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 3:
MicroBlaze Signal Interface Description
AXI4 and ACE Interface Description
Memory Mapped Interfaces
Peripheral Interfaces
The MicroBlaze AXI4 memory mapped peripheral interfaces are implemented as 32-bit masters.
Each of these interfaces only have a single outstanding transaction at any time, and all transactions
are completed in order.
•
The instruction peripheral interface (M_AXI_IP) only performs single word read accesses, and
is always set to use the AXI4-Lite subset.
•
The data peripheral interface (M_AXI_DP) performs single word accesses, and is set to use the
AXI4-Lite subset as default, but is set to use AXI4 when enabling exclusive access for LWX
and SWX instructions. Halfword and byte writes are performed by setting the appropriate byte
strobes.
Cache Interfaces
The AXI4 and ACE memory mapped cache interfaces are implemented either as 32-bit, 128-bit,
256-bit, or 512-bit masters, depending on cache line length and data width parameters.
•
With a 32-bit master, the instruction cache interface (M_AXI_IC or M_ACE_IC) performs 4
word or 8 word burst read accesses, depending on cache line length. With 128-bit, 256-bit, or
512-bit masters, only single read accesses are performed.
This interface can have multiple outstanding transactions, issuing up to 2 transactions or up to
5 transactions when stream cache is enabled. The stream cache can request two cache lines in
advance, which means that in some cases 5 outstanding transactions can occur. When stream
cache is enabled,
C_INTERCONNECT_M_AXI_IC_READ_ISSUING
is set to 8, since it must
be a power of two.
How memory locations are accessed depend on the parameter
C_ICACHE_ALWAYS_USED
. If
the parameter is 1, the cached memory range is always accessed via the AXI4 or ACE cache
interface. If the parameter is 0, the cached memory range is accessed over the AXI4 periperal
interface when the caches are software disabled (that is, MSR[ICE]=0).
•
With a 32-bit master, the data cache interface (M_AXI_DC or M_ACE_DC) performs single
word accesses, as well as 4 word or 8 word burst accesses, depending on cache line length.
Burst write accesses are only performed when using write-back cache. With 128-bit, 256-bit,
or 512-bit masters, only single accesses are performed.
This interface can have multiple outstanding transactions, either issuing up to 2 transactions
when reading, or up to 32 transactions when writing. MicroBlaze ensures that all outstanding
writes are completed before a read is issued, since the processor must maintain an ordered
memory model but AXI or ACE has separate read/write channels without any ordering. Using
up to 32 outstanding write transactions improves performance, since it allows multiple writes to
proceed without stalling the pipeline.
Word, halfword and byte writes are performed by setting the appropriate byte strobes.
Exclusive accesses can be enabled for LWX and SWX instructions.
How memory locations are accessed depend on the parameter
C_DCACHE_ALWAYS_USED
. If
the parameter is 1, the cached memory range is always accessed via the AXI4 or ACE cache
interface. If the parameter is 0, the cached memory range is accessed over the AXI4 periperal
interface when the caches are software disabled (that is, MSR[DCE]=0).
