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XAUI v12.3 Product Guide

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PG053 April 6, 2016

Chapter 9

Test Bench

This chapter contains information about the provided test bench in the Vivado® Design

Suite.

The demonstration test bench is designed to exercise the example design. It uses the MDIO

management interface to determine when the core is initialized and ready for use and then

sends some simple frames in both Tx and Rx directions.

The test bench is supplied as part of the Example Simulation output product group.

X-Ref Target - Figure 9-1

Figure 9

‐

Demonstration Test Bench

Clock

Generation

Stimulus

Monitor

MDIO Interface

Stimulus

Monitor

Transceivers

XAUI Encrypted HDL

Clock Logic

Reset Logic

Reg

Out

Support

Clocking

demo_tb

<component_name>_example_design

X13671

Send Feedback

Summary of Contents for LogiCORE IP

Page 1: ...XAUI v12 3 LogiCORE IP Product Guide Vivado Design Suite PG053 April 6 2016...

Page 2: ...gning with the Core Use the Example Design as a Starting Point 70 Know the Degree of Difficulty 70 Keep It Registered 71 Recognize Timing Critical Signals 71 Use Supported Design Flows 71 Make Only Al...

Page 3: ...aining the Core 109 Simulation 111 Synthesis and Implementation 111 Chapter 8 Detailed Example Design Chapter 9 Test Bench Appendix A Verification and Interoperability Simulation 119 Hardware Testing...

Page 4: ...XAUI v12 3 Product Guide www xilinx com 4 PG053 April 6 2016 Revision History 141 Please Read Important Legal Notices 142 Send Feedback...

Page 5: ...8 State Machines Available under the Xilinx End User License Agreement IP Facts LogiCORE IP Facts Core Specifics Supported Device Family 1 1 For a complete list of supported devices see Vivado IP cata...

Page 6: ...omponents in a 10 Gigabit Ethernet system distributed across a circuit board and to reduce the number of interface signals in comparison with the XGMII 10 Gigabit Ethernet Media Independent Interface...

Page 7: ...Core with Client Side User Logic X13667 FPGA User Logic Transceiver Transceiver Transceiver Transceiver Clocks and Reset Logic Idle Generation Synchronization Deskew Management Synchronization Synchro...

Page 8: ...e latest IP Update on the Xilinx IP Center For detailed information about the core see the XAUI product page Recommended Design Experience Although the XAUI core is a fully verified solution the chall...

Page 9: ...ns of XAUI have extended beyond 10 Gigabit Ethernet to the backplane and other general high speed interconnect applications Figure 1 3 shows a typical backplane and other general high speed interconne...

Page 10: ...r License Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page For information about pricing and availability of other Xilinx LogiCORE IP m...

Page 11: ...t the XAUI core submit a webcase from Xilinx Support web page Be sure to include the following information Product name Core version number Explanation of your comments Document For comments or sugges...

Page 12: ...t transceiver user guide Transmit Path Latency As measured from the input port xgmii_txd 63 0 of the transmitter side XGMII until that data appears on the txdata pins on the internal transceiver inter...

Page 13: ...erface Speed Grades The minimum device requirements for 10G and 20G operation are listed in the following table Resource Utilization UltraScale Architecture Devices Table 2 2 provides approximate reso...

Page 14: ...ximate resource counts for the various core options on Artix 7 FPGAs Table 2 3 Device Utilization Virtex 7 FPGAs Shared Logic MDIO Management LUTs FFs In Example Design FALSE 1036 1193 In Example Desi...

Page 15: ...regain of alignment Frame transmission Frame reception Clock compensation Recovery from error conditions Hardware Verification The core has been used in several hardware test platforms within Xilinx I...

Page 16: ...rxd 63 0 OUT clk156_out Received data eight bytes wide xgmii_rxc 7 0 OUT clk156_out Receive control bits one bit per received data byte Table 2 7 Ports Corresponding to the I O of the Transceiver Sign...

Page 17: ...Status Ports 7 Series FPGAs Signal Name Direction Clock Domain Description CHANNEL 0 GT0 DRP gt0_drpaddr 8 0 in dclk DRP address bus for channel 0 gt0_drpen in dclk DRP enable signal 0 No read or writ...

Page 18: ...t Async GTXE2 and GTPE2 This active High PLL frequency lock signal indicates that the PLL frequency is within predetermined tolerance Signal Integrity and Functionality GT0 Eye scan gt0_eyescantrigger...

Page 19: ...tter post cursor TX pre emphasis control gt0_txdiffctrl_in 3 0 in Async Driver Swing Control gt0_txinhibit_in in clk156_out When High this signal blocks the transmission of data GT0 PRBS gt0_rxprbscnt...

Page 20: ...1 Write operation when drpen is 1 gt1_drp_busy out dclk GTPE2 all configurations or GTHE2 10G configuration Indicates the DRP interface is being used internally by the serial transceiver and should no...

Page 21: ...he polarity of incoming data gt1_txpolarity_in in clk156_out The txpolarity port can invert the polarity of outgoing data GT1 RX Decision Feedback Equalizer DFE gt1_rxlpmen_in in Async GTXE2 and GTHE2...

Page 22: ...ntains errors GT1 RX CDR gt1_rxcdrhold_in in Async Hold the CDR control loop frozen GT1 Digital Monitor gt1_dmonitorout_out 7 0 out Async GTXE2 Digital Monitor Output Bus gt1_dmonitorout_out 14 0 out...

Page 23: ...A reset process gt2_rxpcsreset_in in Async Starts the RX PCS reset process gt2_rxpmaresetdone_out out Async GTHE2 and GTPE2 This active High signal indicates RX PMA reset is complete gt2_rxresetdone_o...

Page 24: ...GTPE2 Determines whether the value of the high frequency boost is either held or adapted gt2_rxlpmhfovrden_in in Async GTPE2 Determines whether the high frequency boost is controlled by an attribute o...

Page 25: ...alid character in the 8B 10B table gt2_rxcommadet_out out clk156_out This signal is asserted when the comma alignment block detects a comma CHANNEL 3 GT3 DRP gt3_drpaddr 8 0 in dclk DRP address bus fo...

Page 26: ...alignment initialization done gt3_txdlysresetdone_out out Async TX delay alignment soft reset done gt3_cplllock_out out Async GTHE2 This active High PLL frequency lock signal indicates that the PLL fr...

Page 27: ...t3_txpostcursor_in 4 0 in Async Transmitter post cursor TX post emphasis control gt3_txprecursor_in 4 0 in Async Transmitter post cursor TX pre emphasis control gt3_txdiffctrl_in 3 0 in Async Driver S...

Page 28: ...0 No read or write operation performed 1 enables a read or write operation gt0_drpdi 15 0 in dclk Data bus for writing configuration data to the transceiver for channel 0 gt0_drpdo 15 0 out dclk Data...

Page 29: ...DRP address bus for channel 3 gt3_drpen in dclk DRP enable signal 0 No read or write operation performed 1 enables a read or write operation gt3_drpdi 15 0 in dclk Data bus for writing configuration d...

Page 30: ...e Signal Integrity and Functionality Eye Scan gt_eyescantrigger 3 0 in clk156_out Causes a trigger event gt_eyescanreset 3 0 in Async This port is driven High and then deasserted to start the EYESCAN...

Page 31: ...sticky status output indicates that PRBS errors have occurred gt_rxprbssel 15 0 in clk156_out Receiver PRBS checker test pattern control gt_txprbssel 15 0 in clk156_out Transmitter PRBS generator tes...

Page 32: ...k156_out MDIO 3 state 1 disconnects the output driver from the MDIO bus type_sel 1 0 in Tie off Type select prtad 4 0 in Tie off MDIO port address you should set this to provide a unique ID on the MDI...

Page 33: ...12 5 MHz for 20G XAUI operation clk156_lock out This active High PLL frequency lock signal indicates that the PLL frequency is within predetermined tolerance The transceiver and its clock outputs are...

Page 34: ...esses 1 and 3 in the MDIO register address map as shown in Table 2 14 Table 2 14 10GBASE X PCS PMA MDIO Registers Register Address Register Name 1 0 Physical Medium Attachment Physical Medium Dependen...

Page 35: ...complete The soft_reset pin is connected to this bit This can be connected to the reset of any other MMDs R W Self clearing 0 1 0 14 Reserved The block always returns 0 for this bit and ignores writes...

Page 36: ...serial transceivers back into the receiver R W 0 X Ref Target Figure 2 2 Figure 2 2 PMA PMD Status 1 Register Table 2 16 PMA PMD Status 1 Register Bit Definitions Bit Name Description Attributes Defa...

Page 37: ...Speed Ability X Ref Target Figure 2 3 Figure 2 3 PMA PMD Device Identifier Registers Table 2 17 PMA PMD Device Identifier Registers Bit Definitions Bit Name Description Attributes Default Value 1 2 15...

Page 38: ...G Capable The block always returns 1 for this bit and ignores writes R O 1 X Ref Target Figure 2 5 Figure 2 5 PMA PMD Devices in Package Registers Table 2 19 PMA PMD Devices in Package Registers Bit D...

Page 39: ...O 0 1 5 1 PMA PMD Present The block always returns 1 for this bit R O 1 1 5 0 Clause 22 Device Present The block always returns 0 for this bit R O 0 X Ref Target Figure 2 6 Figure 2 6 10G PMA PMD Cont...

Page 40: ...ns 0 for this bit R O 0 1 8 10 Receive Fault The block always returns 0 for this bit R O 0 1 8 9 Reserved The block always returns 0 for this bit R O 0 1 8 8 PMD Transmit Disable Ability The block alw...

Page 41: ...ions Bit Name Description Attributes Default Value 1 10 15 5 Reserved The block always returns 0s for these bits R O All 0s 1 10 4 PMD Receive Signal OK 3 1 Signal OK on receive Lane 3 0 Signal not OK...

Page 42: ...obal PMD Receive Signal OK 1 Signal OK on all receive lanes 0 Signal not OK on all receive lanes R O X Ref Target Figure 2 9 Figure 2 9 PMA PMD Package Identifier Registers Table 2 23 PMA PMD Package...

Page 43: ...s writes R O 0 3 0 13 Speed Selection The block always returns 1 for this bit and ignores writes R O 1 3 0 12 Reserved The block always returns 0 for this bit and ignores writes R O 0 3 0 11 Power dow...

Page 44: ...al fault detected 0 No local fault detected This bit is set to 1 whenever either of the bits 3 8 11 3 8 10 are set to 1 R O 3 1 6 3 Reserved The block always returns 0s for these bits and ignores writ...

Page 45: ...Speed Ability X Ref Target Figure 2 12 Figure 2 12 PCS Device Identifier Registers Table 2 26 PCS Device Identifier Registers Bit Definition Bit Name Description Attributes Default Value 3 2 15 0 PCS...

Page 46: ...es writes R O All 0s 3 4 0 10G Capable The block always returns 1 for this bit and ignores writes R O 1 X Ref Target Figure 2 14 Figure 2 14 PCS Devices in Package Registers Table 2 28 PCS Devices in...

Page 47: ...WIS Present The block always returns 0 for this bit R O 0 3 5 1 PMA PMD Present The block always returns 1 for this bit R O 1 3 5 0 Clause 22 device present The block always returns 0 for this bit R O...

Page 48: ...fault 1 Fault condition on transmit path 0 No fault condition on transmit path R O Latching High Self clears after a read unless the fault is still present 3 8 10 Receive local fault 1 Fault condition...

Page 49: ...re 2 17 Figure 2 17 Package Identifier Registers Table 2 31 PCS Package Identifier Register Bit Definitions Bit Name Description Attributes Default Value 3 14 15 0 Package Identifier The block always...

Page 50: ...10GBASE X receive lanes aligned 0 10GBASE X receive lanes not aligned RO 3 24 11 Pattern Testing Ability The block always returns 1 for this bit R O 1 3 24 10 4 Reserved The block always returns 0 fo...

Page 51: ...ister Bit Definitions Bit Name Description Attributes Default Value 3 25 15 3 Reserved The block always returns 0 for these bits R O All 0s 3 25 2 Transmit Test Pattern Enable 1 Transmit test pattern...

Page 52: ...4 DTE XS MDIO Registers Register Address Register Name 5 0 DTE XS Control 1 5 1 DTE XS Status 1 5 2 5 3 DTE XS Device Identifier 5 4 DTE XS Speed Ability 5 5 5 6 DTE XS Devices in Package 5 7 Reserved...

Page 53: ...peed Selection The block always returns 1 for this bit and ignores writes R O 1 5 0 12 Reserved The block always returns 0 for this bit and ignores writes R O 0 5 0 11 Power down 1 Power down mode 0 N...

Page 54: ...ault detected This bit is set to 1 whenever either of the bits 5 8 11 5 8 10 are set to 1 R O 5 1 6 3 Reserved The block always returns 0s for these bits and ignores writes R O All 0s 5 1 2 DTE XS Rec...

Page 55: ...tributes Default Value 5 2 15 0 DTE XS Identifier The block always returns 0 for these bits and ignores writes R O All 0s 5 3 15 0 DTE XS Identifier The block always returns 0 for these bits and ignor...

Page 56: ...esent The block always returns 0 for this bit R O 0 5 6 13 0 Reserved The block always returns 0 for these bits R O All 0s 5 6 15 6 Reserved The block always returns 0 for these bits R O All 0s 5 5 5...

Page 57: ...ent The block always returns 10 R O 10 5 8 13 12 Reserved The block always returns 0 for these bits R O All 0s 5 8 11 Transmit Local Fault 1 Fault condition on transmit path 0 No fault condition on tr...

Page 58: ...available High frequency test pattern of 1010101010 at each device specific transceiver output Low frequency test pattern of 111110000011111000001111100000 at each device specific transceiver output m...

Page 59: ...ns Bit Name Description Attributes Default Value 5 24 15 13 Reserved The block always returns 0 for these bits R O All 0s 5 24 12 DTE XGXS Lane Alignment Status 1 DTE XGXS receive lanes aligned 0 DTE...

Page 60: ...t Control Register RSVD TEST PATTERN ENABLE TEST PATTERN SELECT 15 3 2 1 0 Reg 5 25 X13718 Table 2 43 10G DTE XGXS Test Control Register Bit Definitions Bit Name Description Attributes Default Value 5...

Page 61: ...Table 2 44 PHY XS MDIO Registers Register Address Register Name 4 0 PHY XS Control 1 4 1 PHY XS Status 1 4 2 4 3 Device Identifier 4 4 PHY XS Speed Ability 4 5 4 6 Devices in Package 4 7 Reserved 4 8...

Page 62: ...peed Selection The block always returns 1 for this bit and ignores writes R O 1 4 0 12 Reserved The block always returns 0 for this bit and ignores writes R O 0 4 0 11 Power down 1 Power down mode 0 N...

Page 63: ...ault detected This bit is set to 1 whenever either of the bits 4 8 11 4 8 10 are set to 1 R O 4 1 6 3 Reserved The block always returns 0s for these bits and ignores writes R O All 0s 4 1 2 PHY XS Rec...

Page 64: ...Attributes Default Value 4 2 15 0 PHY XS Identifier The block always returns 0 for these bits and ignores writes R O All 0s 4 3 15 0 PHY XS Identifier The block always returns 0 for these bits and ig...

Page 65: ...Bit Definitions Bit Name Description Attributes Default Value 4 6 15 Vendor specific Device 2 present The block always returns 0 for this bit R O 0 4 6 14 Vendor specific Device 1 present The block al...

Page 66: ...Definitions Bit Name Description Attributes Default Value 4 8 15 14 Device Present The block always returns 10 R O 10 4 8 13 12 Reserved The block always returns 0 for these bits R O All 0s 4 8 11 Tr...

Page 67: ...5 Figure 2 35 PHY XS Package Identifier Registers PACKAGE IDENTIFIER 15 0 Reg 4 15 PACKAGE IDENTIFIER 15 0 Reg 4 14 X13707 Table 2 51 Package Identifier Registers Bit Definitions Bit Name Description...

Page 68: ...es not aligned RO 4 24 11 PatternTesting Ability The block always returns 1 for this bit R O 1 4 24 10 4 Reserved The block always returns 0 for these bits R O All 0s 4 24 3 Lane 3 Sync 1 Lane 3 is sy...

Page 69: ...nsmit test pattern enable 0 Transmit test pattern disabled R W 0 4 25 1 0 Test Pattern Select 11 Reserved 10 Mixed frequency test pattern 01 Low frequency test pattern 00 High frequency test pattern R...

Page 70: ...arting Point Each instance of the XAUI core is delivered with an example design that can be implemented in an FPGA and simulated This design can be used as a starting point for your own design or can...

Page 71: ...constraint file provided with the example design for the core identifies the critical signals and the timing constraints that should be applied See Chapter 8 Constraining the Core for further informa...

Page 72: ...nsmission Special code groups are used to allow each lane to synchronize at a word boundary and to deskew all four lanes into alignment at the receiving end The XAUI standard is fully specified in cla...

Page 73: ...applications A typical backplane application is shown in Figure 4 2 X Ref Target Figure 4 1 Figure 4 1 Connecting XAUI to an Optical Module X Ref Target Figure 4 2 Figure 4 2 Typical Backplane Applica...

Page 74: ...mit idle generation logic Creates the code groups to allow synchronization and alignment at the receiver Synchronization state machine one per lane Identifies byte boundaries in incoming serial data D...

Page 75: ...AUI Core with Client Side User Logic X13667 FPGA User Logic Transceiver Transceiver Transceiver Transceiver Clocks and Reset Logic Idle Generation Synchronization Deskew Management Synchronization Syn...

Page 76: ...ide on a single rising clock edge This demultiplexing is done by extending the bus upwards so that there are now eight lanes of data numbered 0 7 the lanes are organized such that data appearing on la...

Page 77: ...rror and others These control characters all have in common that the control line for that lane is 1 for the character and a certain data byte value The relevant characters are defined in the IEEE Std...

Page 78: ...ame can be marked by the occurrence of a Start character in lane 0 with the data characters in lanes 1 to 7 When the frame is complete it is completed by a Terminate character the T in lane 1 of Figur...

Page 79: ...e letter E with the relevant control bits set X Ref Target Figure 5 2 Figure 5 2 Frame Transmission with Error Across Internal 64 bit Client Side I F xgmii_txd 7 0 xgmii_txd 15 8 xgmii_txd 23 16 xgmii...

Page 80: ...either lane 0 or in lane 4 The Terminate character T can occur in any lane Figure 5 4 shows an inbound frame of data propagating an error In this instance the error is propagated in lanes 4 to 7 shown...

Page 81: ...with Error Across the Internal 64 bit Client Interface clk156 xgmii_rxd 7 0 xgmii_rxd 15 8 xgmii_rxd 23 16 xgmii_rxd 31 24 xgmii_rxd 39 32 xgmii_rxd 47 40 xgmii_rxd 55 48 xgmii_rxd 63 56 xgmii_rxc 7 0...

Page 82: ...hronization status These ports are described in Debug Port MDIO Interface The Management Data Input Output MDIO interface is a simple low speed two wire interface for management of the XAUI core consi...

Page 83: ...e 5 6 illustrates the use of a Virtex 7 FPGA SelectIO interface 3 state buffer as the bus interface Table 5 3 MDIO Management Interface Port Description Signal Name Direction Description mdc IN Manage...

Page 84: ...the PRTAD field set to a value other than that on its prtad 4 0 port MDIO Transactions The MDIO interface should be driven from a STA master according to the protocol defined in IEEE Std 802 3 2012 An...

Page 85: ...takes the 16 bit word in the data field and writes it to the register at the current address X Ref Target Figure 5 7 Figure 5 7 MDIO Set Address Transaction Z 1 1 1 0 0 0 P4 P3 P2 P1 P0 V4 V3 V2 V1 V...

Page 86: ...ess This allows sequential reading or writing by a STA master of a block of register addresses X Ref Target Figure 5 9 Figure 5 9 MDIO Read Transaction Z 1 1 1 0 1 1 P4 P3 P2 P1 P0 V4 V3 V2 V1 V0 Z 0...

Page 87: ...cific transceivers See bit 5 0 14 in Table 2 35 1 Power Down Sets the device specific transceivers into power down mode See bit 5 0 11 in Table 2 35 2 Reset Local Fault Clears both TX Local Fault and...

Page 88: ...otherwise 0 see bit 5 8 10 in Table 2 40 Latches High Cleared by rising edge on configuration_vector 2 5 2 Synchronization Each bit is 1 if the corresponding XAUI lane is synchronized on receive othe...

Page 89: ...orts signaling the alignment and synchronization status of the receiver Table 5 7 Table 5 7 Debug Port Port Name Description debug 5 align_status 1 when the XAUI receiver is aligned across all four la...

Page 90: ...rence clock in the example design as it was in previous versions or inside the core simplifying the design This new level of hierarchy receives the name of component_name _support Figure 6 1 and Figur...

Page 91: ...reset initialization circuitry The dclk clock must not be derived from any transceiver output clocks The frequency of dclk must be entered into the core GUI prior to core generation this frequency in...

Page 92: ...ple design or alternatively inside the core See Figure 6 3 and Figure 6 4 respectively for the shared logic to be included in the example design or in the core X Ref Target Figure 6 3 Figure 6 3 Clock...

Page 93: ...Guide UG576 Ref 3 UltraScale Device GTY Transceivers A single IBUFDS_GTE3 module is used to feed the reference clock to the GTYE3_COMMON transceiver The IBUFDS_GTE3 is included in the Shared Logic lev...

Page 94: ...Scheme for Internal Client Side Interface UltraScale Architecture GTY Transceiver Shared Logic in Example Design Shareable logic 7 B 20021 75 43 287 43 2875 7 B 11 43 5 43 7 865 7 865 5 865 5 865 7 2...

Page 95: ...er logic of a different XAUI core due to problems of phase alignment For more information about UltraScale device transceiver clock distribution see the UltraScale Architecture GTY Transceivers User G...

Page 96: ...requency is flexible the example design uses a 50 MHz clock Choosing a different frequency can allow for the sharing of DRPCLK across all transceivers in a device The dclk clock provided to the core m...

Page 97: ...or alternatively inside the core See Figure 6 7 and Figure 6 8 respectively for the shared logic to be included in the example design or in the core X Ref Target Figure 6 7 Figure 6 7 Clock Scheme fo...

Page 98: ...ifferent XAUI core due to problems of phase alignment For more information about 7 series FPGA transceiver clock distribution see the section on Clocking in the 7 Series FPGAs GTX GTH Transceiver User...

Page 99: ...he core See Figure 6 9 and Figure 6 10 respectively for the shared logic to be included in the example design or in the core X Ref Target Figure 6 9 Figure 6 9 Clock Scheme for Internal Client Side In...

Page 100: ...lems of phase alignment For more information about 7 series FPGA transceiver clock distribution see the section on Clocking in the 7 Series FPGAs GTX GTH Transceiver User Guide UG476 Ref 1 X Ref Targe...

Page 101: ...igure 6 12 respectively for the shared logic to be included in the example design or in the core X Ref Target Figure 6 11 Figure 6 11 Clock Scheme for Internal Client Side Interface 7 Series FPGA GTP...

Page 102: ...ment For more information about 7 series FPGA transceiver clock distribution see the section on clocking in the 7 Series FPGAs GTP Transceiver User Guide UG482 Ref 2 X Ref Target Figure 6 12 Figure 6...

Page 103: ...clock can be shared from a neighboring quad Logic clocks cannot be shared between core instances with the supplied design The usrclks on each core and quad of transceivers are sourced from the TXOUTCL...

Page 104: ...es Full details on that maximum amount of transmit skew can be found by looking at TLLSKEW in the appropriate device data sheet Under some circumstances it is possible that TLLSKEW can exceed the PMA...

Page 105: ...ng with IP UG896 Ref 5 Vivado Design Suite User Guide Getting Started UG910 Ref 6 Vivado Design Suite User Guide Logic Simulation UG900 Ref 7 Customizing and Generating the Core You can customize the...

Page 106: ...20G XAUI Data Rates Transceiver Type This option is only available for Virtex UltraScale devices that contain both GTHE3 and GTYE3 transceivers please select the transceiver type for these devices XAU...

Page 107: ...le devices DRP Clock Frequency MHz Enter the frequency of the DRP clock the dclk input of the core For UltraScale 7 Series and Zync 7000 devices this value is used to set the target frequency for Out...

Page 108: ...Target Figure 7 2 Figure 7 2 Shared Logic Tab Table 7 1 GUI Parameter to User Parameter Relationship GUI Parameter Value 1 User Parameter Value 1 Default Value MDIO Management Mdio_Management true Dat...

Page 109: ...onstraints such as DCLK frequency and Transceiver location should be applied in the user XDC Clock Frequencies A constraint specifying the frequency of the clock 156 25 MHz for 10G or 312 5 MHz for 20...

Page 110: ...Customization GUI before generating the core For GTYE3 transceivers replace the GTHE3 string with GTYE3 and the gthe3 string with gtye3 in the following example syntax set_property LOC GTHE3_CHANNEL_X...

Page 111: ...C GTHE3_CHANNEL_X0Y2 get_cells xaui_i inst xaui_block_i CompName _gt_i gen_gtwizard_gthe3_top CompName _gt_gtwizard_gthe3_inst gen_gtwizard_gthe3 gen_channel_container gen_enabled_channel gthe3_channe...

Page 112: ...2 PG053 April 6 2016 Chapter 7 Design Flow Steps All synthesis sources are included that are required by the core For the XAUI core this is a mix of both encrypted and unencrypted source Only the unen...

Page 113: ...ample Design 7 Series FPGAs X13673 component_name_gt_wrapper vhd v Transceiver component_name_gt_wrapper_gt vhd v Transceiver component_name_gt_wrapper_gt vhd v Transceiver component_name_gt_wrapper_g...

Page 114: ...ic in Core 7 Series FPGAs X13672 component_name_gt_wrapper vhd v Transceiver component_name_gt_wrapper_gt vhd v Transceiver component_name_gt_wrapper_gt vhd v Transceiver component_name_gt_wrapper_gt...

Page 115: ...d Logic in the Example Design UltraScale Architecture component_name_gt UltraScale wizard subcore XAUI Encrypted HDL Clock Logic component_name_clk_clocking vhd v Reset Logic component_name_clk_resets...

Page 116: ...be placed directly on a board and does not constrain the I O pins The example design can be opened in a separate project by generating the Examples output product then right clicking the core instanc...

Page 117: ...determine when the core is initialized and ready for use and then sends some simple frames in both Tx and Rx directions The test bench is supplied as part of the Example Simulation output product grou...

Page 118: ...O monitor to check when the core is ready to send receive frames The demonstration test bench performs the following tasks Clocks are generated An initial reset is applied The MDIO interface is addres...

Page 119: ...e transmission Frame reception Clock compensation Recovery from error conditions Hardware Testing The core has been used in several hardware test platforms within Xilinx In particular the core has bee...

Page 120: ...egated into a single port For example gt0_gtrxreset and gt1_gtrxreset now become gt_gtrxreset 1 0 This is true for all ports with the exception of the DRP buses which follow the convention of gt n _dr...

Page 121: ...ug port The ports related to the drp interface drp_addr drp_en drp_i drp_o drp_rdy drp_we are now split into four sets one for each transceiver and are only available when the Transceiver Control and...

Page 122: ...interface moved to Transceiver Control and Status Ports Use gt0_drpi gt1_drpi gt2_drpi gt3_drpi drp_o 63 0 OUT DRP interface moved to Transceiver Control and Status Ports Use gt0_drpo gt1_drpo gt2_drp...

Page 123: ...and Status Ports GTX and GTH transceivers only Assign default value 0 gtN_rxdfelpmreset_in IN Added Transceiver Control and Status Ports GTX and GTH transceivers only Assign default value 0 gtN_rxmon...

Page 124: ...n Table B 3 Ports Added when the Transceiver Control and Status Ports Option is Enabled N is the number of the channel Cont d Port Direction Reason for Change Proposed Solution Table B 4 Ports Added F...

Page 125: ...ol and Status Ports Assign default value open gtN_rxcommadet_out out Added Transceiver Control and Status Ports Assign default value open Table B 4 Ports Added From v12 0 to v12 1 Cont d Port Directio...

Page 126: ...inx Support web page contains key resources such as product documentation release notes answer records and links for obtaining further product support Documentation This product guide is the main docu...

Page 127: ...mes error messages or a generic summary of the issue encountered To see all answer records directly related to the XAUI core search for the phrase XAUI Master Answer Record for the XAUI core AR 54666...

Page 128: ...ignals can then be analyzed This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx The Vivado logic analyzer is used to interact with the logic debug L...

Page 129: ...cific open a case with Xilinx Technical Support and include a wlf file dump of the simulation For the best results dump the entire design hierarchy If using VHDL do you have a mixed mode simulation li...

Page 130: ...mulation To discuss possible solutions use the Xilinx User Community forums xilinx com xlnx Hardware Debug Hardware issues can range from link bring up to problems seen after hours of testing This sec...

Page 131: ...nterface is encoded to be a randomized sequence of K Sync R Skip A Align codes on the XAUI interface For more information on this encoding see the IEEE 802 3 2012 specification section 48 2 4 2 for mo...

Page 132: ...ault below Check that the core is correctly configured using either the configuration vector or the MDIO interface Monitor XGMII data and data on Rocket IO interface Are errors being inserted by the X...

Page 133: ...he receiver is being reset At least one of the lanes is not synchronized debug 4 1 The lanes are not properly aligned debug 5 Note The debug 5 0 signal is not latching A TX local fault is indicated in...

Page 134: ...silently drop any data being transmitted and instead transmit a remote fault RX Link Status 0 link down in Device A X Ref Target Figure C 3 Stage 2 Device B Powers Up and Resets Device B powers up an...

Page 135: ...in Figure C 6 Device A and Device B have both powered up and been reset The link status is 1 link up in both A and B and in both the MAC can transmit frames successfully X Ref Target Figure C 6 Figur...

Page 136: ...rs are seen or if an A code is not seen in all four lanes at the same time See the following section Problems with a High Bit Error Rate Transceiver Specific Ensure that the polarities of the txn txp...

Page 137: ...e does not meet the specification Problems with a High Bit Error Rate Symptoms If the link comes up but then goes down again or never comes up following a reset the most likely cause for a RX Local Fa...

Page 138: ...ect operation in the transceiver parallel loopback but not in serial loopback this might indicate a transceiver issue A mild form of bit error rate might be solved by adjusting the transmitter Pre Emp...

Page 139: ...rt assist with the issue To create a technical support case in Webcase see the Xilinx website at www xilinx com support clearexpress websupport htm Items to include when opening a case Detailed descri...

Page 140: ...r User Guide UG482 3 UltraScale Architecture GTH Transceivers User Guide UG576 4 Ultrascale Architecture GTY Transceivers User Guide UG578 5 Vivado Design Suite User Guide Designing with IP UG896 6 Vi...

Page 141: ...Hampshire Interoperability Lab is an excellent source of information on 10 Gigabit Ethernet technology www iol unh edu consortiums 10gec index html Revision History The following table shows the revis...

Page 142: ...to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Term...

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