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KC724 IBERT Getting 
Started Guide (Vivado 
Design Suite 2012.3)

UG931 (v1.0) October 23, 2012

This document applies to the following software versions: Vivado Design Suite 2012.3 and 2012.4

This document applies to the following software versions: Vivado Design Suite 2012.3 and 2012.4

This document applies to the following software versions: Vivado Design Suite 2012.3 and 2012.4

This document applies to the following software versions: Vivado Design Suite 2012.3 and 2012.4

Summary of Contents for KC724 IBERT

Page 1: ...e versions Vivado Design Suite 2012 3 and 2012 4 This document applies to the following software versions Vivado Design Suite 2012 3 and 2012 4 This document applies to the following software versions...

Page 2: ...g your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a res...

Page 3: ...7 Connecting the GTX Transceivers and Reference Clocks 7 Attach the GTX Quad Connector 10 GTX Transceiver Clock Connections 10 GTX TX RX Loopback Connections 11 Configuring the FPGA 12 Setting Up the...

Page 4: ...4 www xilinx com KC724 IBERT Getting Started Guide UG931 v1 0 October 23 2012...

Page 5: ...ored in a Secure Digital SD memory card that is provided with the KC724 board The demonstration shows the capabilities of the Kintex 7 XC7K325T FPGA GTX transceiver The KC724 board is described in det...

Page 6: ...Design Suite Setting Up the KC724 Board This section describes how to set up the KC724 board Caution The KC724 board can be damaged by electrostatic discharge ESD Follow standard ESD prevention measu...

Page 7: ...q118 cpj These files are used to load pre saved MGT IBERT and SuperClock 2 module control settings for the IBERT demonstrations To copy the files from the Secure Digital memory card 1 Connect the Secu...

Page 8: ...m KC724 IBERT Getting Started Guide UG931 v1 0 October 23 2012 Chapter 1 KC724 IBERT Getting Started Guide X Ref Target Figure 1 1 Figure 1 1 GTX Quad Locations UG931_c1_01_080812 QUAD_116 QUAD_115 QU...

Page 9: ...k outputs from the Si5368 clock multiplier jitter attenuator device on the clock module The SMA pair labeled Si570_CLK provides LVDS clock output from the Si570 programmable oscillator on the clock mo...

Page 10: ...aligning the two indexing pins on the bottom of the connector with the guide holes on the board Hold the connector flush with the board and fasten it by tightening the two captive screws GTX Transceiv...

Page 11: ...RX0 RX1 RX2 and RX3 and the four transmitters TX0 TX1 TX2 and TX3 Use eight SMA female to female F F adapters Figure 1 6 to connect the transmit and receive cables as shown in Figure 1 7 and detailed...

Page 12: ...at http www xilinx com kc724 To configure from the SD card 1 Insert the SD card provided with the KC724 board into the SD card reader slot located on the bottom side upper right corner of the KC724 b...

Page 13: ...design for each GTX Quad on the KC724 board for a total of four IBERT designs Four other demonstration designs are included that show other board features the use of these designs are described in the...

Page 14: ...apter 1 KC724 IBERT Getting Started Guide Setting Up the ChipScope Pro Software 1 Start Vivado design suite on the host computer and click Open Project icon highlighted in Figure 1 10 X Ref Target Fig...

Page 15: ...er 23 2012 Running the GTX IBERT Demonstration 2 In the Open Project window Figure 1 11 navigate to the project_1 directory created when Extracting the Project Files Select project_1 xpr and click OK...

Page 16: ...e Open Project 5 When the Project window opens navigate to the directory where the ChipScope software project files cpj were extracted Select kc724_q115 cpj and click Open Note The cpj file loads pre...

Page 17: ...e an integrated ChipScope Pro software VIO core to control the clocks on the SuperClock 2 module The SuperClock 2 module features two clock source components 1 An always on Si570 crystal oscillator an...

Page 18: ...nd Si570 devices i e Si5368 ROM Addr and Si570 ROM Addr are preset to 19 to produce an output frequency of 125 000 MHz Entering a different ROM address changes the reference clock s frequency The comp...

Page 19: ...demonstration is configured and running The status and test settings are displayed on the MGT IBERT Settings tab in the IBERT Console shown in Figure 1 18 Note the line rate TX differential output swi...

Page 20: ...simply reset the counter click the respective BERT Reset button Figure 1 19 to zero the count If the MGT Link Status shows No Link for one or more transceivers click the respective TX Reset button fo...

Page 21: ...ting File Exit Note Do not save changes to the project 2 Place the main power switch SW1 in the off position Additional information on the ChipScope Pro software and IBERT core can be found in UG029 C...

Page 22: ...10 CPRI 491 520 40 OTU 1 666 750 70 Generic 666 667 11 Display Port 67 500 41 OTU 2 167 330 71 Generic 205 000 12 Display Port 81 000 42 OTU 2 669 310 72 Generic 210 000 13 Display Port 135 000 43 OT...

Page 23: ...00 95 Generic 325 000 108 Generic 390 000 121 Generic 455 000 96 Generic 330 000 109 Generic 395 000 122 Generic 460 000 97 Generic 335 000 110 Generic 400 000 123 Generic 465 000 98 Generic 340 000 1...

Page 24: ...e GTX Quads with any supported line rate can be created following the same series of steps For more details on generating IBERT cores refer to UG029 ChipScope Pro Software Cores 1 Start the Vivado tes...

Page 25: ...IBERT Getting Started Guide www xilinx com 25 UG931 v1 0 October 23 2012 Creating the GTX IBERT Core X Ref Target Figure 1 22CORE Generator Figure 1 22 Project Name and Location Fields UG931_c1_22_10...

Page 26: ...RT Getting Started Guide 5 In the Project Type window verify RTL Project the default is selected Click Next Figure 1 23 6 For each of the next three windows Add Sources Add Existing IP and Add Constra...

Page 27: ...UG931 v1 0 October 23 2012 Creating the GTX IBERT Core 7 In the Default Part window adjust the filter as shown in Figure 1 24 to select the xc7k325tffg00900 3 device then click Next X Ref Target Figur...

Page 28: ...ing Started Guide UG931 v1 0 October 23 2012 Chapter 1 KC724 IBERT Getting Started Guide 8 Review the New Project Summary window and click Finish Figure 1 25 X Ref Target Figure 1 25 Figure 1 25 New P...

Page 29: ...Started Guide www xilinx com 29 UG931 v1 0 October 23 2012 Creating the GTX IBERT Core 9 Click IP Catalog under the Project Manager tab Figure 1 26 X Ref Target Figure 1 26 Figure 1 26 IP Catalog Icon...

Page 30: ...ERT Getting Started Guide 10 In the IP Catalog pane of the Project Manager window Figure 1 27 select Debug Verification Debug IBERT 7 Series GTX ChipScope Pro IBERT 2 02 a Double click the selected co...

Page 31: ...ds page 1 of the IP customization window will appear For Component Name type ibert_k7_q115 and under Board Configuration Settings select kc724 scm2 Then uncheck the Generate Bitstream using ISE tools...

Page 32: ...pter 1 KC724 IBERT Getting Started Guide 12 Enter the information shown here and in Figure 1 29 then click Next No of Quads 1 Select Quad QUAD 115 Max Rate Gbps 12 5 Refclk MHz 125 000 GT count 4 X Re...

Page 33: ...g the GTX IBERT Core 13 Enter the information shown here and in Figure 1 30 then click Next MGT0_115 CUSTOM1 12 5 Gbps MGT1_115 CUSTOM1 12 5 Gbps MGT2_115 CUSTOM1 12 5 Gbps MGT3_115 CUSTOM1 12 5 Gbps...

Page 34: ...KC724 IBERT Getting Started Guide 14 Enter the information shown here and in Figure 1 31 then click Next MGT0_115 MGTREFCLK1 115 MGT1_115 MGTREFCLK1 115 MGT2_115 MGTREFCLK1 115 MGT3_115 MGTREFCLK1 11...

Page 35: ...ctober 23 2012 Creating the GTX IBERT Core 15 Verify the information shown in Figure 1 32 then click Generate The Customize IP status bar will appear on screen for a few seconds X Ref Target Figure 1...

Page 36: ...ears on screen select the XCO file under Design Sources within the Sources pane of the Project Manager window right click the XCO file and select Generate Output Products Figure 1 33 17 When the Manag...

Page 37: ...KC724 IBERT Getting Started Guide www xilinx com 37 UG931 v1 0 October 23 2012 Creating the GTX IBERT Core X Ref Target Figure 1 34 Figure 1 34 Manage Outputs UG931_c1_34_100812...

Page 38: ...irectory by entering this command in the Tcl Console Figure 1 35 cd C vivado_work project_1 project_1 srcs sources_1 ip chipsco pe_ibert_7series_gtx_v2_02_a_0 ibert_k7_q115 implement Note The parent p...

Page 39: ...3 2012 Creating the GTX IBERT Core 19 To take the project through the rest of the RDS and RDI implementation flow to generate a bitstream enter source v_rdi_implement tcl Figure 1 36 X Ref Target Figu...

Page 40: ...Bitstream Generation Completed dialog window appears click Cancel Figure 1 37 21 When the Synthesis Completed dialog window appears click Cancel Figure 1 38 X Ref Target Figure 1 37 Figure 1 37 Bitst...

Page 41: ...cation Figure 1 39 23 When the exit confirmation window appears click OK Figure 1 40 24 Navigate to the C vivado_work project_1 project_1 runs impl_1 directory to locate the resultant bitstream X Ref...

Page 42: ...42 www xilinx com KC724 IBERT Getting Started Guide UG931 v1 0 October 23 2012 Chapter 1 KC724 IBERT Getting Started Guide...

Page 43: ...eglect or default of Customer For any breach by Xilinx of this limited warranty the exclusive remedy of Customer and the sole liability of Xilinx shall be at the option of Xilinx to replace or repair...

Page 44: ...44 www xilinx com KC724 IBERT Getting Started Guide UG931 v1 0 October 23 2012 Appendix A Warranty...

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