Xilinx FMC XM104, User Manual, Page: 10 / 21

10 www.xilinx.com FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
Chapter 1: XM104
Board Technical Description
The XM104 provides a number of connectors which break out the FPGA multi-gigabit
transceiver (MGT) interface signals to and from the board interface.
Figure 1-2 shows a
block diagram of the XM104. Each MGT data port interface consists of two differential
pairs of MGT signals, one pair for the transmitter and one pair for the receiver. MGT Data
Ports 0 and 1 are each wired to four SMA connectors. MGT Data Ports 2 and 3 are each
wired to host Serial ATA connectors J11 and J12 respectively. MGT Data Ports 4 through 7
are wired to a 10GE Base-CX4 connector supporting a XAUI application interface. MGT
transmitter Data Ports 8 and 9 are electrically looped back to the board receiver ports 8 and
9 respectively. The ML605 does not support Data Port 8 and 9 interfaces.
Silicon Laboratories Si570 serial IIC bus reprogrammable LVDS clock source and a Si5368
any-rate precision clock multiplier and jitter attenuator integrated circuits provide a
variety of programmable differential clock sources to the board’s FGPA. The Si5368
integrated circuit receives three differential LVDS clock inputs from the board and outputs
five LVDS differential clock outputs to the FPGA.
A 2 Kb serial IIC EEPROM is also connected to the IIC interface of the board providing
non-volatile storage. The serial IIC interface also connects to the Si570 and Si5368
integrated circuits enabling the board’s FPGA to program the clock circuitry on the XM104.
X-Ref Target - Figure 1-2
Figure 1-2: XM104 Block Diagram
UG5 3 6_02_120 3 09
2 K b
EEPROM
S i5 3 68
Any-r a te Clock
S i570
Clock
156.25 MHz
Clock
Driver
Level
S hifter
IIC
IIC
S witch
GBTCLK1_M2C
GBTCLK0_M2C
CLK1_M2C
CLK2_M2C
CLK 3 _M2C
LA00_CC
LA01_CC
LA17_CC
MGT D a t a Port 0
S MA (4x)
DP0
DP1
DP2
DP 3
DP4-DP7
DP8-DP9
MGT D a t a Port 1
S MA (4x)
MGT D a t a Port 2
S eri a l ATA J11
MGT D a t a Port 3
S eri a l ATA J12
MGT D a t a Port s 4-7
10GE B as e-CX4 J2
J1 FMC HPC Interf a ce
MGT D a t a Port s 8-9
Electric a l Loop ba ck
CLK0_M2C
J 3 , J4, J5, J6
J7, J8, J9, J10
F S _OUT
CKOUT1
CKOUT2
CKOUT 3
CKOUT4
CKIN1
CKIN2
CKIN 3
CKIN4