Xilinx FMC XM104, User Manual, Page: 19 / 21

FMC XM104 Connectivity Card User Guide www.xilinx.com 19
UG536 (v1.1) September 24, 2010
Board Technical Description
Silicon Labs Si536 8
A Silicon Labs Si5368 any-rate precision clock multiplier/jitter attenuator integrated
circuit provides a wide range of clocking applications for the Xilinx board and XM104
combination.
Table 1-13 shows the connections of the SI5368 differential clock outputs to
the XM104 FMC HPC connector. Table 1-13 also shows connections of the clock outputs
from the board to the inputs of the SI5368.
Table 1-13: Si5368 Clock I/O Connections to FMC HPC Connector J1
FMC Connector J1
Pin
Signal Name I/O Standard Si5368 In/Out Si5368
H4 CLK0_M2C_P LVDS
Output
CKOUT5/FS_OUT_P
H5 CLK0_M2C_N LVDS CKOUT5/FS_OUT_N
G2 CLK1_M2C_P LVDS
Output
CKOUT2_P
G3 CLK1_M2C_N LVDS CKOUT2_N
K4 CLK2_M2C_P LVDS
Output
CKOUT3_P
K5 CLK2_M2C_N LVDS CKOUT3_N
J2 CLK3_M2C_P LVDS
Output
CKOUT4_P
J3 CLK3_M2C_N LVDS CKOUT4_N
D4 GBTCLK0_M2C_P LVDS
Output
CKOUT1_P
D5 GBTCLK0_M2C_N LVDS CKOUT1_N
G6 LA00_CC_P LVDS
Input
CKIN1_P
G8 LA00_CC_N LVDS CKIN1_N
- CLK_SI570_P LVDS
Input
CKIN2_P
- CLK_SI570_N LVDS CKIN2_N
D8 LA01_CC_P LVDS
Input
CKIN3_P
D9 LA01_CC_N LVDS CKIN3_N
D20 LA17_CC_P LVDS
Input
CKIN4_P
D21 LA17_CC_N LVDS CKIN4_N
G13 LA08_N LVCMOS_Vadj Input C2A
G12 LA08_P LVCMOS_Vadj Input C1A
H14 LA07_N LVCMOS_Vadj I/O CS1_C4A
(1)
H13 LA07_P LVCMOS_Vadj Input INC
C11 LA06_N LVCMOS_Vadj Input DEC
C10 LA06_P LVCMOS_Vadj Output LOL
D11 LA05_P LVCMOS_Vadj Input FS_ALIGN
H12 LA04_N LVCMOS_Vadj I/O CS0_C3A
(1)
H10 LA04_P LVCMOS_Vadj Output INT_ALM