Xilinx FMC XM104, User Manual, Page: 15 / 21

FMC XM104 Connectivity Card User Guide www.xilinx.com 15
UG536 (v1.1) September 24, 2010
Board Technical Description
6. Multi-Gigabit Transceiver Data Ports [4:7] - J2 10GE Base-CX4 Connector
Board FPGA multi-gigabit transceiver Data Ports 4 through 7 are wired to a 10GE Base-
CX4 connector J2 on the XM104. The four data port connections between the XM104 FMC
HPC connector and the 10G Base-CX4 connector J2 are defined in
Table 1-7 .
7. 2 Kb EEPROM
An STMicroelectronics M24C02 2 Kb serial IIC bus EEPROM component provides a small
amount of non-volatile memory storage on the XM104. The IIC interface is connected
directly to the board’s IIC interface as shown in
Figure 1-2, page 10 .
The IIC address of this component is controlled by a combination of the board’s interface
and chip enable connections to the component inputs on the XM104. Signals GA0 and GA1
from the board are connected to the chip enable inputs of the M24C02 component enables
E0 and E1. Xilinx boards provide GA0 and GA1 signal strapping to 3.3V and GND signals
creating different E0 and E1 chip enable decodes on the E1 and E0 inputs of the EEPROM.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4 bit Device Type Identifier and a 3-bit Chip Enable Address (E2, E1 and
E0). Bit 0 is used to indicate read/write. The Device Type Identifier for the EEPROM is 1010
binary.
Table 1-8 defines the generic EEPROM Device Select Code as well as specific Device
Code Select addresses of the EEPROM when the XM104 is connected to a Xilinx board
defined in
Table 1-1, page 7 .
The M24C02 component data sheet is available online at www.st.com .
Table 1-7: FPGA Multi-Gigabit Transceiver Data Ports 4 - 7 Connectivity
FMC HPC
Connector J1 Pin
Signal Name
J2 Connector Pin
(Receiver)
FMC HPC
Connector J1 Pin
Signal Name
J2 Connector Pin
(Transmitter)
A14 DP4_M2C_P
(1)
S1 B33 DP7_C2M_N S9
A15 DP4_M2C_N
(1)
S2 B32 DP7_C2M_P S10
A18 DP5_M2C_P
(1)
S3 B37 DP6_C2M_N S11
A19 DP5_M2C_N
(1)
S4 B36 DP6_C2M_P S12
B16 DP6_M2C_P
(1)
S5 A39 DP5_C2M_N S13
B17 DP6_M2C_N
(1)
S6 A38 DP5_C2M_P S14
B12 DP7_M2C_P
(1)
S7 A35 DP4_C2M_N S15
B13 DP7_M2C_N
(1)
S8 A34 DP4_C2M_P S16
Notes:
1. All receiver signals are AC coupled using 0.1 uF series capacitors
Table 1-8: EEPROM IIC Device Select Code
Bit 7:4 Device
Type Identifier
Bit 3 Bit 2 Bit 1 Bit 0 LSB Description
1010 0 GA0 GA1 Read/Write
Connected to mezzanine FMC HPC
interface