Xilinx EK-U1-VCU128-G-J User Manual Download Page 49 | Manualshive

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Jitter Attenuated Clock

, callout 17]

The VCU128 board includes a Silicon Labs Si5328B jitter attenuator U87 on the back side of the
board. FPGA U1 bank 67 implements two QSFP RX differential clocks (QSFP1_RECCLK_P, pin
BH26 and QSFP1_RECCLK_N, pin BH25, and QSFP2_RECCLK_P, pin BJ26 and
QSFP2_RECCLK_N, pin BK25) for jitter attenuation.

The jitter attenuated clock pair (SI5328_CLOCK1_C_P (U87 output pin 28),
SI5328_CLOCK1_C_N (U87 output pin 29) is routed as a reference clock to FPGA U1 QSFP2 I/F
GTY Quad 134 inputs MGTREFCLK1P (U1 pin R40) and MGTREFCLK1N (U1 pin R41).

The jitter attenuated clock pair (SI5328_CLOCK2_C_P (U87 output pin 35),
SI5328_CLOCK2_C_N (U87 output pin 34) is routed as a reference clock to FPGA U1 QSFP3 I/F
GTY Quad 132 inputs MGTREFCLK1P (U1 pin W40) and MGTREFCLK1N (U1 pin W41).

The primary purpose of this clock is to support synchronous protocols, such as common packet
radio interface (CPRI) or open base station architecture initiative (OBSAI). These synchronous
protocols perform clock recovery from user-supplied QSFP/QSFP+ modules, and use the jitter
attenuated recovered clock to drive the reference clock inputs of a GTY transceiver.

The jitter attenuated clock circuit is shown in the following figure.

Figure 19: QSFP Recovery Clock

X21968-121918

Chapter 3: Board Component Descriptions

UG1302 (v1.1) April 21, 2021

VCU128 Board User Guide

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Summary of Contents for EK-U1-VCU128-G-J

Page 1: ...VCU128 Evaluation Board User Guide UG1302 v1 1 April 21 2021 ...

Page 2: ...g the Board in a PC Chassis 14 FPGA Configuration 16 Chapter 3 Board Component Descriptions 18 Overview 18 Component Descriptions 18 Appendix A VITA 57 4 FMCP Connector Pinouts 93 Overview 93 Appendix B Xilinx Constraints File 94 Overview 94 Appendix C Regulatory and Compliance Information 95 Overview 95 CE Directives 95 CE Standards 95 Compliance Markings 96 Appendix D Additional Resources and Le...

Page 3: ...Xilinx Resources 97 Documentation Navigator and Design Hubs 97 References 98 Please Read Important Legal Notices 100 UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 3 Send Feedback ...

Page 4: ... Revision Summary 04 21 2021 Version 1 1 Board Power System Revised the Renesas smart power stage module part number in the power system block diagram 12 21 2018 Version 1 0 Initial release N A Revision History UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 4 Send Feedback ...

Page 5: ...th many of the common board level features needed for design development as listed here DDR4 RLD 3 and QDR IV component memory Ganged small form factor pluggable QSFP28 connectors Sixteen lane PCI Express interface Ethernet PHY General purpose I O UART interface Additional features can be supported using modules compatible with the VITA 57 4 FMCP HSPC connector on the VCU128 board Additional Resou...

Page 6: ...BTCLK4 FMCP_HSPC_DP 12 15 FMCP_HSPC_GBTCLK3 FMCP_HSPC_DP 8 11 FMCP_HSPC_GBTCLK2 FMCP_HSPC_DP 4 7 FMCP_HSPC_GBTCLK1 FMCP_HSPC_DP 0 3 FMCP_HSPC_GBTCLK0 72 bit DDR4 Comp Memory 4 5X512MX16 MT40A512M16LY 075E GPIO 1 8V ENET LED 0 7 PL_I2C0 BUS UART0 UART1 QSFP1 QSFP4 CTRL SMA_CLK OUT P N SYSCTLR_UCA1 TX RX 36 bit DQA port common 36 bit QDR IV SDRAM 4Mx36 Dual Port CY7C4142KV13_106FCXC 36 bit DQB port ...

Page 7: ...00 MHz LVDS clock oscillators PCIe I F clock Fixed 100 MHz HCSL clock from PCI Express edge input to 1 to 2 clock buffer wired to GTY225 and GTY227 System controller clock SiT8008A 33 33 MHz single ended clock oscillator 96 GTY transceivers 24 Quads FMCP HSPC connector twenty four GTY transceivers 4x28 Gb s QSFP connectors eight GTY transceivers PCIe 16 lane edge connector sixteen GTY transceivers...

Page 8: ...ed connector Board Specifications Dimensions Height 7 53 inch 19 14 cm Length 9 50 inch 24 13 cm Thickness 5 0 061 inch 0 1549 cm Note A 3D model of this board is not available IMPORTANT The VCU128 board height exceeds the standard 4 376 inch 11 15 cm height of a PCI Express card Environmental Temperature Operating 0 C to 45 C Storage 25 C to 60 C Humidity 10 to 90 non condensing Operating Voltage...

Page 9: ...do not have a wrist strap before you remove the product from ESD packaging and installing or replacing hardware touch an unpainted metal surface of the system for a minimum of five seconds Do not remove the device from the antistatic bag until you are ready to install the device in the system With the device still in its antistatic bag touch it to the metal frame of the system Grasp cards and boar...

Page 10: ...t This document is not intended to be a reference design guide and the information herein should not be used as such Always refer to the schematic layout and XDC files of the specific VCU128 version of interest for such details Figure 2 Evaluation Board Component Locations 33 27 38 24 32 40 39 30 8 6 29 25 00 Round callout references a component on the front side of the board Square callout refere...

Page 11: ... 50 9 System Controller Quad SPI Flash Memory U89 Micron MT25QU02GCBB8E12 0SIT 49 10 DDR4 Component Memory I F clock fixed 100 MHz LVDS U76 SiTime SIT9120AI 2D3 33E100 0000 32 11 RLD3 Component Memory I F clock fixed 100 MHz LVDS U45 SiTime SIT9120AI 2D3 33E100 0000 32 12 QDR4 Component Memory I F clock fixed 100 MHz LVDS U96 SiTime SIT9120AI 2D3 33E100 0000 32 13 Programmable QSFP1 Clock I2C LVDS...

Page 12: ... 29 User GPIO pushbutton CPU reset SW4 active High E Switch TL3301EF100QG 47 30 Switches program_B pushbutton SW2 active Low E Switch TL3301EF100QG 3 31 FMCP Connector J18 J18 Samtec ASP_184329_01 42 46 32 Board Power System Power Input Connector J16 2x6 Molex 39 30 1060 52 33 Board Power System power input switch on off slide switch SW5 C K 1201M2S3AQE2 52 34 Board Power System power management s...

Page 13: ...A U1 XCVU37P USER P B active high 29 47 Notes 1 DIP switch sections are active High connected net is pulled High when DIP switch is closed 1 Jumpers Default jumper settings are listed in the following table Jumper header locations are shown in Figure 2 The following table also references the respective schematic page numbers Table 3 Default Jumper Settings Jumper Function Default Comments Figure 2...

Page 14: ...ality When the VCU128 board is used inside a computer chassis i e plugged in to a PCIe slot power is provided by choosing one of two mutually exclusive ATX power supply cables as described in this section use one cable or the other The ATX power supply 4 pin 1x4 peripheral connector which requires using the ATX adapter cable see the following figure to connect to J16 on the VCU128 board The Xilinx...

Page 15: ... on the top and bottom of the cover 6 Plug the VCU128 board into the appropriate open slot 7 Install the top mounting bracket screw into the PC expansion cover retainer bracket to secure the VCU128 board in its slot 8 If using the ATX supply 4 pin 1x4 peripheral connector connect power to the VCU128 board using the ATX power supply adapter cable as shown in the previous figure a Plug the 6 pin 2 x...

Page 16: ... bus widths as listed in the following table The mode switches M2 M1 and M0 are on SW1 positions 2 3 and 4 respectively The FPGA default mode setting M 2 0 001 selects the master SPI configuration mode Table 4 Configuration Modes Configuration Mode SW1 DIP Switch Settings M 2 0 Bus Width CCLK Direction Master SPI 1 x1 x2 x4 Output JTAG 101 x1 NA For complete details on configuring the FPGA see Ult...

Page 17: ... a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI flash device U46 connected to the FPGA bank 0 Quad SPI interface See the VCU128 Restoring Flash Tutorial XTP533 for information on programming the QSPI 2 Set the boot mode pins SW1 M 2 0 as indicated in the configuration modes table in FPGA Configuration for master SPI 3 Power cycle the VCU128 board Mode SW1 is callout 36 in Figure 2 See the ...

Page 18: ...andwidth memory HBM FPGA which utilizes stacked silicon interconnect SSI technology to add HBM die next to the FPGA die on the package substrate The VCU128 board is populated with the Virtex UltraScale XCVU37P 2FSVH2892E device For more information on Virtex UltraScale FPGAs see Virtex UltraScale FPGA Data Sheet DC and AC Switching Characteristics DS923 Encryption Key Battery Backup Circuit The XC...

Page 19: ...V I O Voltage Rails There are 12 I O banks and 2 high bandwidth memory HBM banks available on the XCVU37P device The VCU128 board does not use the HBM banks The voltages applied to the FPGA I O banks on the VCU128 board are listed in the following table Table 5 I O Bank Voltage Rails FPGA U1 Bank Power Supply Rail Net Name Voltage Bank 0 VCC1V8 1 8V HP bank 64 DDR4_VDDQ_1V2 1 2V HP bank 65 DDR4_VD...

Page 20: ...5E Description 8 Gb 512 Mb x 16 1 2V 96 ball TFBGA DDR4 2666 The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex UltraScale FPGA Data Sheet DC and AC Switching Characteristics DS923 The 72 bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64 65 and 66 The DDR4 0 6V VTT termination voltage net DDR4_VTERM_0V6 is sourced from the TI TPS51200DR linear regulator...

Page 21: ..._DCI H8 DQ5 U17 BL42 PL_DDR4_DQ14 POD12_DCI J3 DQ6 U17 BJ43 PL_DDR4_DQ15 POD12_DCI J7 DQ7 U17 BK45 PL_DDR4_DQS1_T DIFF_POD12_DCI G3 LDQS_T U17 BK46 PL_DDR4_DQS1_C DIFF_POD12_DCI F3 LDQS_C U17 BL47 PL_DDR4_DM1_B POD12_DCI E7 NF LDM_B LDBI_B U17 BK41 PL_DDR4_DQ16 POD12_DCI G2 DQ0 U74 BG44 PL_DDR4_DQ17 POD12_DCI F7 DQ1 U74 BG42 PL_DDR4_DQ18 POD12_DCI H3 DQ2 U74 BH44 PL_DDR4_DQ19 POD12_DCI H7 DQ3 U74 ...

Page 22: ...DDR4_DM4_B POD12_DCI E7 NF LDM_B LDBI_B U73 BL32 PL_DDR4_DQ40 POD12_DCI G2 DQ0 U19 BP34 PL_DDR4_DQ41 POD12_DCI F7 DQ1 U19 BN34 PL_DDR4_DQ42 POD12_DCI H3 DQ2 U19 BK33 PL_DDR4_DQ43 POD12_DCI H7 DQ3 U19 BL31 PL_DDR4_DQ44 POD12_DCI H2 DQ4 U19 BL33 PL_DDR4_DQ45 POD12_DCI H8 DQ5 U19 BM33 PL_DDR4_DQ46 POD12_DCI J3 DQ6 U19 BK31 PL_DDR4_DQ47 POD12_DCI J7 DQ7 U19 BL35 PL_DDR4_DQS5_T DIFF_POD12_DCI G3 LDQS_T...

Page 23: ...69 POD12_DCI C8 DQ13 U17 BN49 PL_DDR4_DQ70 POD12_DCI D3 DQ14 U17 BL51 PL_DDR4_DQ71 POD12_DCI D7 DQ15 U17 BM49 PL_DDR4_DQS8_T DIFF_POD12_DCI B7 UDQS_T U17 BM50 PL_DDR4_DQS8_C DIFF_POD12_DCI A7 UDQS_C U17 BP48 PL_DDR4_DM8_B POD12_DCI E2 NF UDM_B UDBI_B U17 COMMON BF50 PL_DDR4_A0 SSTL12_DCI P3 A0 U17 U19 U73 U74 BD51 PL_DDR4_A1 SSTL12_DCI P7 A1 U17 U19 U73 U74 BG48 PL_DDR4_A2 SSTL12_DCI R3 A2 U17 U19...

Page 24: ... U19 U73 U74 BH49 PL_DDR4_ODT SSTL12_DCI K3 ODT U17 U19 U73 U74 BP49 PL_DDR4_CS_B SSTL12_DCI L7 CS_B U17 U19 U73 U74 The VCU128 DDR4 memory component interfaces adhere to the constraints guidelines documented in the DDR3 DDR4 Design Guidelines section of the UltraScale Architecture Based FPGAs Memory IP LogiCORE IP Product Guide PG150 The VCU128 board DDR4 memory component interface is a 40Ω imped...

Page 25: ...DQ1 SSTL12 E10 DQ1 U39 K32 RLD3_72B_DQ2 SSTL12 C8 DQ2 U39 J31 RLD3_72B_DQ3 SSTL12 C10 DQ3 U39 L29 RLD3_72B_DQ4 SSTL12 C12 DQ4 U39 L31 RLD3_72B_DQ5 SSTL12 B9 DQ5 U39 L30 RLD3_72B_DQ6 SSTL12 B11 DQ6 U39 J32 RLD3_72B_DQ7 SSTL12 A8 DQ7 U39 K31 RLD3_72B_DQ8 SSTL12 A10 DQ8 U39 G30 RLD3_72B_DQ9 SSTL12 J10 DQ9 U39 H30 RLD3_72B_DQ10 SSTL12 K11 DQ10 U39 F31 RLD3_72B_DQ11 SSTL12 K13 DQ11 U39 G28 RLD3_72B_DQ1...

Page 26: ...7 H40 RLD3_72B_DQ42 SSTL12 B11 DQ6 U37 J40 RLD3_72B_DQ43 SSTL12 A8 DQ7 U37 J41 RLD3_72B_DQ44 SSTL12 A10 DQ8 U37 D44 RLD3_72B_DQ45 SSTL12 J10 DQ9 U37 F45 RLD3_72B_DQ46 SSTL12 K11 DQ10 U37 F44 RLD3_72B_DQ47 SSTL12 K13 DQ11 U37 D46 RLD3_72B_DQ48 SSTL12 L8 DQ12 U37 F46 RLD3_72B_DQ49 SSTL12 L10 DQ13 U37 E44 RLD3_72B_DQ50 SSTL12 L12 DQ14 U37 E46 RLD3_72B_DQ51 SSTL12 M9 DQ15 U37 G45 RLD3_72B_DQ52 SSTL12 ...

Page 27: ... F10 A4 U37 U39 K37 RLD3_72B_A5 SSTL12 F12 A5 U37 U39 C38 RLD3_72B_A6 SSTL12 G3 A6 U37 U39 E36 RLD3_72B_A7 SSTL12 F1 A7 U37 U39 B35 RLD3_72B_A8 SSTL12 G11 A8 U37 U39 L35 RLD3_72B_A9 SSTL12 F13 A9 U37 U39 D34 RLD3_72B_A10 SSTL12 H13 A10 U37 U39 E39 RLD3_72B_A11 SSTL12 D1 A11 U37 U39 A35 RLD3_72B_A12 SSTL12 H11 A12 U37 U39 C35 RLD3_72B_A13 SSTL12 D13 A13 U37 U39 E37 RLD3_72B_A14 SSTL12 H3 A14 U37 U3...

Page 28: ...D3_72B_QK2_P DIFF_SSTL12 D5 QK2 U39 E32 RLD3_72B_QK2_N DIFF_SSTL12 E6 QK2_B U39 C30 RLD3_72B_QK3_P DIFF_SSTL12 K5 QK3 U39 B31 RLD3_72B_QK3_N DIFF_SSTL12 J6 QK3_B U39 K41 RLD3_72B_QK4_P DIFF_SSTL12 D9 QK0 U37 K42 RLD3_72B_QK4_N DIFF_SSTL12 E8 QK0_B U37 J44 RLD3_72B_QK5_P DIFF_SSTL12 K9 QK1 U37 H44 RLD3_72B_QK5_N DIFF_SSTL12 J8 QK1_B U37 E42 RLD3_72B_QK6_P DIFF_SSTL12 D5 QK2 U37 E43 RLD3_72B_QK6_N D...

Page 29: ...DR data ports Supports concurrent read write transactions on both ports Single address port used to control both data ports 1 2V 361 ball FCBGA Maximum operating frequency of 1066 MHz The VCU128 XCVU37P FPGA QDR IV interface performance is documented in the Virtex UltraScale FPGA Data Sheet DC and AC Switching Characteristics DS923 The 72 bit wide QDR4 memory is connected to XCVU37P U1 HP banks 68...

Page 30: ...10 QDR4_DQA14 E2 DQA14 BM10 QDR4_DQA15 G2 DQA15 BN9 QDR4_DQA16 G4 DQA16 BJ9 QDR4_DQA17 B5 DQA17 BL12 QDR4_DQA18 C12 DQA18 BK14 QDR4_DQA19 B13 DQA19 BJ12 QDR4_DQA20 C14 DQA20 BK15 QDR4_DQA21 D15 DQA21 BL13 QDR4_DQA22 D13 DQA22 BH14 QDR4_DQA23 A16 DQA23 BH15 QDR4_DQA24 F15 DQA24 BJ14 QDR4_DQA25 A14 DQA25 BJ13 QDR4_DQA26 A12 DQA26 BE9 QDR4_DQA27 H17 DQA27 BE10 QDR4_DQA28 H15 DQA28 BG13 QDR4_DQA29 J18...

Page 31: ..._DINVA0 D8 DINVA0 R519 GND 1 QDR4_DINVA1 D12 DINVA1 QDR4 B side Data H15 QDR4_DQB0 U8 DQB0 J15 QDR4_DQB1 V7 DQB1 J12 QDR4_DQB2 U6 DQB2 J11 QDR4_DQB3 T5 DQB3 H14 QDR4_DQB4 T7 DQB4 G13 QDR4_DQB5 W4 DQB5 J14 QDR4_DQB6 P5 DQB6 H12 QDR4_DQB7 W6 DQB7 H13 QDR4_DQB8 W8 DQB8 G11 QDR4_DQB9 M3 DQB9 E12 QDR4_DQB10 M5 DQB10 F10 QDR4_DQB11 L2 DQB11 E11 QDR4_DQB12 L4 DQB12 D10 QDR4_DQB13 V2 DQB13 E9 QDR4_DQB14 R...

Page 32: ...5 DQB35 QDR4 B side Control K14 QDR4_DKB0_P P4 DKB0_P K13 QDR4_DKB0_N P3 DKB0_N C10 QDR4_DKB1_P P16 DKB1_P C9 QDR4_DKB1_N P17 DKB1_N H10 QDR4_QKB0_P U4 QKB0_P G10 QDR4_QKB0_N T3 QKB0_N E13 QDR4_QKB1_P U16 QKB1_P D12 QDR4_QKB1_N T17 QKB1_N D9 QDR4_QVLDB0 U3 QVLDB0 D14 QDR4_QVLDB1 U17 QVLDB1 BL2 QDR4_LDB_N H12 LDB_N BL3 QDR4_RWB_N L10 RWB_N R606 GND 1 QDR4_DINVB0 T8 DINVB0 R602 GND 1 QDR4_DINVB1 T12...

Page 33: ..._N BK1 QDR4_RST_N K18 RST_N QDR4 U40 ZQ_ZT pin W10 is wired to 220Ω R604 to GND Notes 1 Resistors to GND are 100Ω The VCU128 QDR IV dual independent 36 bit bidirectional data port memory component interfaces adhere to the constraints guidelines documented in the QDR IV Design Guidelines section of the UltraScale Architecture Based FPGAs Memory IP LogiCORE IP Product Guide PG150 The VCU128 QDR IV m...

Page 34: ...b of non volatile storage that can be used for configuration and data storage Part number MT25QU02GCBB8E12 0SIT Micron Supply voltage 1 8V Datapath width 4 bits Data rate various depending on single dual quad mode The Quad SPI circuitry is shown in the following figure Figure 7 Quad SPI 2 Gbit Flash Memory X21957 121918 The connections between the Quad SPI flash memory and the XCVU37P FPGA are lis...

Page 35: ... 24 JTAG configuration is provided through a dual function FTDI FT4232HL USB to JTAG UART bridge device U8 where a host computer accesses the VCU128 board JTAG chain through a type A PC host side to micro AB VCU128 board side J2 USB cable A 2 mm JTAG header J4 is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II JTAG initiated configuration takes prio...

Page 36: ...to an open state when the FMC is attached Switch U72 adds an attached FMC to the FPGA JTAG chain as determined by the FMCP_HSPC_PRSNT_M2C_B signal IMPORTANT The attached FMC must implement a TDI to TDO connection through a device or bypass jumper to ensure that the JTAG chain connects to the FPGA U1 The JTAG connectivity on the VCU128 board allows a host computer to download bitstreams to the FPGA...

Page 37: ...1 bank 67 connections Channel C implements 4 wire UART1 level shifted FPGA U1 bank 67 connections Channel D implements 2 wire level shifted SYSCTLR U42 bank 501 connections The USB UART interface circuit is shown in the following figure The FTDI FT4232HL data sheet is available on the Future Technology Devices International Ltd website Figure 9 FTDI USB JTAG UART Circuit X21958 121918 Chapter 3 Bo...

Page 38: ...Hz default QSFP3_SI570_CLOCK_P N QSFP4 clock 156 250 MHz U80 Silicon Labs Si570 3 3V LVDS I2C programmable oscillator 156 250 MHz default QSFP4_SI570_CLOCK_P N SMA GTY REFCLK and User Clock QSFP GTY131 REFCLK1 SMA clock SMA J24 P SMA J26 N Bank 131 series capacitor coupled SMA clock SMA_REFCLK_INPUT_P N FPGA U1 bank 67 GPIO user SMA clock SMA J12 P SMA J13 N Bank 67 QBC direct connect GPIO SMA SMA...

Page 39: ...K_N 1 Y43 SI570 U80 4 QSFP4_SI570_CLOCK_P 1 AB42 SI570 U80 5 QSFP4_SI570_CLOCK_N 1 AB43 SMA GTY REFCLK and User Clock SMA J24 1 SMA_REFCLK_INPUT_P 1 AA40 SMA J26 1 SMA_REFCLK_INPUT_N 1 AA41 SMA J12 1 SMA_CLK_OUTPUT_P 2 BK26 SMA J13 1 SMA_CLK_OUTPUT_N 2 BL25 QSFP1 2 Recovery Clocks SI5328B U87 29 SI5328_CLOCK1_P 1 R40 SI5328B U87 28 SI5328_CLOCK1_P 1 R41 SI5328B U87 35 SI5328_CLOCK2_P 1 W40 SI5328B...

Page 40: ...s series capacitor coupled Fixed frequency oscillator SiTime SIT9120AI 2D3 33E100 0000 100 MHz 0 6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth 3 3V LVDS differential output The DDR4 interface fixed frequency clock circuit is shown in the following figure Figure 10 DDR4 Interface Clock X21959 121918 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU12...

Page 41: ... series capacitor coupled Fixed frequency oscillator SiTime SIT9120AI 2D3 33E100 0000 100 MHz 0 6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth 3 3V LVDS differential output The QDR4 interface fixed frequency clock circuit is shown in the following figure Figure 11 QDR4 Interface Clock X21961 111918 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU128...

Page 42: ...uency oscillator SiTime SIT9120AI 2D3 33E100 0000 100 MHz 0 6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth 3 3V LVDS differential output The RLD3 interface fixed frequency clock circuit is shown in the following figure The SiTime SiT9120AI data sheet is available on the SiTime Corp website Figure 12 RLD3 Interface Clock X21962 111918 Chapter 3 Board Component Descriptions UG1302 v1 1...

Page 43: ... FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VCU128 evaluation board resets the QSFP1 clock to the default frequency of 156 250 MHz Programmable oscillator Silicon Labs Si570BAB0000544DG 10 MHz 810 MHz Frequency tolerance 50 ppm 3 3V LVDS differential output The programmable QSFP1 clock circuit is shown i...

Page 44: ... FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VCU128 evaluation board resets the QSFP2 clock to the default frequency of 156 250 MHz Programmable oscillator Silicon Labs Si570BAB0000544DG 10 MHz 810 MHz Frequency tolerance 50 ppm 3 3V LVDS differential output The programmable QSFP2 clock circuit is shown i...

Page 45: ... FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VCU128 evaluation board resets the QSFP3 clock to the default frequency of 156 250 MHz Programmable oscillator Silicon Labs Si570BAB0000544DG 10 MHz 810 MHz Frequency tolerance 50 ppm 3 3V LVDS differential output The programmable QSFP3 clock circuit is shown i...

Page 46: ...r FPGA implemented user IP can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VCU128 evaluation board resets the QSFP4 clock to the default frequency of 156 250 MHz Programmable oscillator Silicon Labs Si570BAB0000544DG 10 MHz 810 MHz Frequency tolerance 50 ppm 3 3V LVDS differential output The programmable QSFP4 clock circuit is shown ...

Page 47: ...LK1P pin AA40 with the N side SMA J26 signal SMA_REFCLK_INPUT_N connected to U1 GTY bank 131 MGTREFCLK1N pin AA41 The transceiver reference clock pin absolute input voltage range is 0 5V min to 1 3V max The user SMA MGT clock circuit is shown in the following figure Figure 17 QSFP SMA Clock X21967 121918 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board U...

Page 48: ...N is connected to FPGA U1 HP bank 67 QBC pin BL25 Bank 67 VCC1V8 VCCO is nominally 1 8V Any signal connected to the SMA_CLK_OUTPUT SMA connectors in input mode must be equal to or less than the VCCO for bank 67 This value must be confirmed prior to applying signals to the SMA_CLK_OUTPUT connectors Figure 18 User SMA Clock X22055 121918 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 20...

Page 49: ...k pair SI5328_CLOCK2_C_P U87 output pin 35 SI5328_CLOCK2_C_N U87 output pin 34 is routed as a reference clock to FPGA U1 QSFP3 I F GTY Quad 132 inputs MGTREFCLK1P U1 pin W40 and MGTREFCLK1N U1 pin W41 The primary purpose of this clock is to support synchronous protocols such as common packet radio interface CPRI or open base station architecture initiative OBSAI These synchronous protocols perform...

Page 50: ...ss to 14 of the 24 GTY Quads Four of the GTY Quads are wired to QSFP 1 4 Module Connectors J42 J39 J35 J32 Six of the GTY Quads are wired to FMC HSPC connector DP 0 23 J18 Four of the GTY Quads are wired to the PCIe 16 lane edge connector P1 Ten GTY Quads are not used GTYs 130 133 228 235 The reference clock for a Quad can be sourced from the Quad above or the Quad below the GTY Quad of interest R...

Page 51: ...C_GBTCLK4_M2C_P N NC Four GTY transceivers allocated to FMCP_HSPC_DP 16 19 Quad 127 MGTREFCLK0 FMCP_HSPC_GBTCLK3_M2C_P N NC Four GTY transceivers allocated to FMCP_HSPC_DP 12 15 Quad 126 MGTREFCLK0 FMCP_HSPC_GBTCLK2_M2C_P N NC Four GTY transceivers allocated to FMCP_HSPC_DP 8 11 Quad 125 MGTREFCLK0 FMCP_HSPC_GBTCLK1_M2C_P N NC Four GTY transceivers allocated to FMCP_HSPC_DP 4 7 Quad 124 MGTREFCLK0...

Page 52: ...TX2 RX2 QSFP3_TX3 RX3 QSFP3_TX4 RX4 QSFP3_SI570_CLOCK SI5328_CLOCK2_C BANK 126 MGTY_126_0 MGTY_126_1 MGTY_126_2 MGTY_126_3 MGTY_126_REFCLK0 MGTY_126_REFCLK1 FMCP_HSPC_DP8 FMCP_HSPC_DP9 FMCP_HSPC_DP10 FMCP_HSPC_DP11 FMCP_HSPC_GBTCLK2_M2C NC BANK 131 MGTY_131_0 MGTY_131_1 MGTY_131_2 MGTY_131_3 MGTY_131_REFCLK0 MGTY_131_REFCLK1 QSFP4_TX1 RX1 QSFP4_TX2 RX2 QSFP4_TX3 RX3 QSFP4_TX4 RX4 QSFP4_SI570_CLOCK...

Page 53: ...RXN1_135 QSFP1_RX2_N 21 RX2N C48 MGTYTXP2_135 QSFP1_TX3_P 33 TX3P C49 MGTYTXN2_135 QSFP1_TX3_N 34 TX3N E53 MGTYRXP2_135 QSFP1_RX3_P 14 RX3P E54 MGTYRXN2_135 QSFP1_RX3_N 15 RX3N A49 MGTYTXP3_135 QSFP1_TX4_P 6 TX4P A50 MGTYTXN3_135 QSFP1_TX4_N 5 TX4N D51 MGTYRXP3_135 QSFP1_RX4_P 25 RX4P D52 MGTYRXN3_135 QSFP1_RX4_N 24 RX4N P42 MGTREFCLK0P_135 QSFP_SI570_CLOCK_P1 4 OUT U95 SI570 I2C prog osc P43 MGTR...

Page 54: ...34 QSFP2_TX3_P 33 TX3P K47 MGTYTXN2_134 QSFP2_TX3_N 34 TX3N J53 MGTYRXP2_134 QSFP2_RX3_P 14 RX3P J54 MGTYRXN2_134 QSFP2_RX3_N 15 RX3N J48 MGTYTXP3_134 QSFP2_TX4_P 6 TX4P J49 MGTYTXN3_134 QSFP2_TX4_N 5 TX4N H51 MGTYRXP3_134 QSFP2_RX4_P 25 RX4P H52 MGTYRXN3_134 QSFP2_RX4_N 24 RX4N T42 MGTREFCLK0P_134 QSFP2_SI570_CLOCK_P1 4 OUT U90 SI570 I2C prog osc T43 MGTREFCLK0N_134 QSFP2_SI570_CLOCK_N1 5 OUT_B R...

Page 55: ...P2_132 QSFP3_TX3_P 33 TX3P T47 MGTYTXN2_132 QSFP3_TX3_N 34 TX3N T51 MGTYRXP2_132 QSFP3_RX3_P 14 RX3P T52 MGTYRXN2_132 QSFP3_RX3_N 15 RX3N R44 MGTYTXP3_132 QSFP3_TX4_P 6 TX4P R45 MGTYTXN3_132 QSFP3_TX4_N 5 TX4N R53 MGTYRXP3_132 QSFP3_RX4_P 25 RX4P R54 MGTYRXN3_132 QSFP3_RX4_N 24 RX4N Y42 MGTREFCLK0P_132 QSFP3_SI570_CLOCK_P 1 4 OUT U82 SI570 I2C prog osc Y43 MGTREFCLK0N_132 QSFP3_SI570_CLOCK_N1 5 OU...

Page 56: ...8 MGTYTXP2_131 QSFP4_TX3_P 33 TX3P W49 MGTYTXN2_131 QSFP4_TX3_N 34 TX3N W53 MGTYRXP2_131 QSFP4_RX3_P 14 RX3P W54 MGTYRXN2_131 QSFP4_RX3_N 15 RX3N W44 MGTYTXP3_131 QSFP4_TX4_P 6 TX4P W45 MGTYTXN3_131 QSFP4_TX4_N 5 TX4N V51 MGTYRXP3_131 QSFP4_RX4_P 25 RX4P V52 MGTYRXN3_131 QSFP4_RX4_N 24 RX4N AB42 MGTREFCLK0P_131 QSFP4_SI570_CLOCK_P1 4 OUT U80 SI570 I2C prog osc AB43 MGTREFCLK0N_131 QSFP4_SI570_CLOC...

Page 57: ..._DP21_M2C_N M11 DP21_M2C_N AF46 MGTYTXP2_129 FMCP_HSPC_DP22_C2M_P Z4 DP22_C2M_P AF47 MGTYTXN2_129 FMCP_HSPC_DP22_C2M_N Z5 DP22_C2M_N AE53 MGTYRXP2_129 FMCP_HSPC_DP22_M2C_P M6 DP22_M2C_P AE54 MGTYRXN2_129 FMCP_HSPC_DP22_M2C_N M7 DP22_M2C_N AE44 MGTYTXP3_129 FMCP_HSPC_DP23_C2M_P Y2 DP23_C2M_P AE45 MGTYTXN3_129 FMCP_HSPC_DP23_C2M_N Y3 DP23_C2M_N AE49 MGTYRXP3_129 FMCP_HSPC_DP23_M2C_P M2 DP23_M2C_P AE...

Page 58: ...P17_M2C_N Y35 DP17_M2C_N AJ44 MGTYTXP2_128 FMCP_HSPC_DP18_C2M_P M34 DP18_C2M_P AJ45 MGTYTXN2_128 FMCP_HSPC_DP18_C2M_N M35 DP18_C2M_N AJ53 MGTYRXP2_128 FMCP_HSPC_DP18_M2C_P Z36 DP18_M2C_P AJ54 MGTYRXN2_128 FMCP_HSPC_DP18_M2C_N Z37 DP18_M2C_N AH46 MGTYTXP3_128 FMCP_HSPC_DP19_C2M_P M38 DP19_C2M_P AH47 MGTYTXN3_128 FMCP_HSPC_DP19_C2M_N M39 DP19_C2M_N AH51 MGTYRXP3_128 FMCP_HSPC_DP19_M2C_P Y38 DP19_M2C...

Page 59: ...DP13_M2C_N Z17 DP13_M2C_N AM46 MGTYTXP2_127 FMCP_HSPC_DP14_C2M_P M18 DP14_C2M_P AM47 MGTYTXN2_127 FMCP_HSPC_DP14_C2M_N M19 DP14_C2M_N AM51 MGTYRXP2_127 FMCP_HSPC_DP14_M2C_P Y18 DP14_M2C_P AM52 MGTYRXN2_127 FMCP_HSPC_DP14_M2C_N Y19 DP14_M2C_N AL44 MGTYTXP3_127 FMCP_HSPC_DP15_C2M_P M22 DP15_C2M_P AL45 MGTYTXN3_127 FMCP_HSPC_DP15_C2M_N M23 DP15_C2M_N AL53 MGTYRXP3_127 FMCP_HSPC_DP15_M2C_P Y22 DP15_M2...

Page 60: ...N B5 DP9_M2C_N AR48 MGTYTXP2_126 FMCP_HSPC_DP10_C2M_P Z24 DP10_C2M_P AR49 MGTYTXN2_126 FMCP_HSPC_DP10_C2M_N Z25 DP10_C2M_N AR53 MGTYRXP2_126 FMCP_HSPC_DP10_M2C_P Y10 DP10_M2C_P AR54 MGTYRXN2_126 FMCP_HSPC_DP10_M2C_N Y11 DP10_M2C_N AR44 MGTYTXP3_126 FMCP_HSPC_DP11_C2M_P Y26 DP11_C2M_P AR45 MGTYTXN3_126 FMCP_HSPC_DP11_C2M_N Y27 DP11_C2M_N AP51 MGTYRXP3_126 FMCP_HSPC_DP11_M2C_P Z12 DP11_M2C_P AP52 MG...

Page 61: ..._DP5_M2C_N A19 DP5_M2C_N AV46 MGTYTXP2_125 FMCP_HSPC_DP6_C2M_P B36 DP6_C2M_P AV47 MGTYTXN2_125 FMCP_HSPC_DP6_C2M_N B37 DP6_C2M_N AW49 MGTYRXP2_125 FMCP_HSPC_DP6_M2C_P B16 DP6_M2C_P AW50 MGTYRXN2_125 FMCP_HSPC_DP6_M2C_N B17 DP6_M2C_N AU44 MGTYTXP3_125 FMCP_HSPC_DP7_C2M_P B32 DP7_C2M_P AU45 MGTYTXN3_125 FMCP_HSPC_DP7_C2M_N B33 DP7_C2M_N AV51 MGTYRXP3_125 FMCP_HSPC_DP7_M2C_P B12 DP7_M2C_P AV52 MGTYRX...

Page 62: ...A6 DP2_M2C_P BA54 MGTYRXN2_124 FMCP_HSPC_DP2_M2C_N A7 DP2_M2C_N BA44 MGTYTXP3_124 FMCP_HSPC_DP3_C2M_P A30 DP3_C2M_P BA45 MGTYTXN3_124 FMCP_HSPC_DP3_C2M_N A31 DP3_C2M_N BA49 MGTYRXP3_124 FMCP_HSPC_DP3_M2C_P A10 DP3_M2C_P BA50 MGTYRXN3_124 FMCP_HSPC_DP3_M2C_N A11 DP3_M2C_N AV42 MGTREFCLK0P_124 FMCP_HSPC_GBTCLK0_M2C_P1 D4 GBTCLK0_M2C_P AV43 MGTREFCLK0N_124 FMCP_HSPC_GBTCLK0_M2C_N1 D5 GBTCLK0_M2C_N AT...

Page 63: ...CLK1 NC BANK 226 MGTY_226_0 MGTY_226_1 MGTY_226_2 MGTY_226_3 MGTY_226_REFCLK0 MGTY_226_REFCLK1 PCIE_EP_TX RX_7 PCIE_EP_TX RX_6 PCIE_EP_TX RX_5 PCIE_EP_TX RX_4 NC NC BANK 224 MGTY_224_0 MGTY_224_1 MGTY_224_2 MGTY_224_3 MGTY_224_REFCLK0 MGTY_224_REFCLK1 PCIE_EP_TX RX_15 PCIE_EP_TX RX_14 PCIE_EP_TX RX_13 PCIE_EP_TX RX_12 NC NC X21651 092618 Left side GTY Transceiver Connectivity The following tables ...

Page 64: ...P2 AN5 MGTYRXN1_227 PCIE_EP_RX2_N B24 PETN2 AM9 MGTYTXP2_227 PCIE_EP_TX1_P A21 PERP1 AM8 MGTYTXN2_227 PCIE_EP_TX1_N A22 PERN1 AM4 MGTYRXP2_227 PCIE_EP_RX1_P B19 PETP1 AM3 MGTYRXN2_227 PCIE_EP_RX1_N B20 PETN1 AL11 MGTYTXP3_227 PCIE_EP_TX0_P A16 PERP0 AL10 MGTYTXN3_227 PCIE_EP_TX0_N A17 PERN0 AL2 MGTYRXP3_227 PCIE_EP_RX0_P B14 PETP0 AL1 MGTYRXN3_227 PCIE_EP_RX0_N B15 PETN0 AL15 MGTREFCLK0P_227 PCIE_...

Page 65: ..._226 PCIE_EP_RX6_P B41 PETP6 AT3 MGTYRXN1_226 PCIE_EP_RX6_N B42 PETN6 AR7 MGTYTXP2_226 PCIE_EP_TX5_P A39 PERP5 AR6 MGTYTXN2_226 PCIE_EP_TX5_N A40 PERN5 AR2 MGTYRXP2_226 PCIE_EP_RX5_P B37 PETP5 AR1 MGTYRXN2_226 PCIE_EP_RX5_N B38 PETN5 AR11 MGTYTXP3_226 PCIE_EP_TX4_P A35 PERP4 AR10 MGTYTXN3_226 PCIE_EP_TX4_N A36 PERN4 AP4 MGTYRXP3_226 PCIE_EP_RX4_P B33 PETP4 AP3 MGTYRXN3_226 PCIE_EP_RX4_N B34 PETN4 ...

Page 66: ...8 PETP10 AW1 MGTYRXN1_225 PCIE_EP_RX10_N B59 PETN10 AV9 MGTYTXP2_225 PCIE_EP_TX9_P A56 PERP9 AV8 MGTYTXN2_225 PCIE_EP_TX9_N A57 PERN9 AW6 MGTYRXP2_225 PCIE_EP_RX9_P B54 PETP9 AW5 MGTYRXN2_225 PCIE_EP_RX9_N B55 PETN9 AU7 MGTYTXP3_225 PCIE_EP_TX8_P A52 PERP8 AU6 MGTYTXN3_225 PCIE_EP_TX8_N A53 PERN8 AV4 MGTYRXP3_225 PCIE_EP_RX8_P B50 PETP8 AV3 MGTYRXN3_225 PCIE_EP_RX8_N B51 PETN8 AR15 MGTREFCLK0P_225...

Page 67: ...24 PCIE_RX13_N B71 PETN13 BA11 MGTYTXP3_224 PCIE_TX12_P A68 PERP12 BA10 MGTYTXN3_224 PCIE_TX12_N A69 PERN12 BA6 MGTYRXP3_224 PCIE_RX12_P B66 PETP12 BA5 MGTYRXN3_224 PCIE_RX12_N B67 PETN12 AV13 MGTREFCLK0P_224 NC NC NC NC AV12 MGTREFCLK0N_224 AT13 MGTREFCLK1P_224 NC NC NC NC AT12 MGTREFCLK1N_224 Notes 1 Series 0 01 µF capacitor coupled PCI Express Endpoint Connectivity Figure 2 callout 20 The 16 la...

Page 68: ...e following figure Figure 22 PCI Express Lane Clock Circuit and Size Select Jumper J46 X21969 112818 The tables in Left side GTY Transceiver Connectivity list the PCIe P1 edge connector wiring to the XCVU37P FPGA U1 MGTY transceiver banks 227 224 The two PCIe P1 edge connector control signals PCIE_EP_WAKE P1 pin B11 and PCIE_EP_PERST P1 pin A11 are level shifted by SN74AVC2T245 U70 and connected t...

Page 69: ... s QSFP cage assembly J37 The following figure shows a typical implementation of the 28 Gb s QSFP28 module connector circuitry Table 12 through Table 15 in Right side GTY Transceiver Connectivity list the QSFP28 connections to the XCVU37P FPGA U1 MGTY transceiver banks 135 QSFP1 134 QSFP2 132 QSFP3 and 131 QSFP4 Figure 23 28 Gb s QSFP28 Module Connector X21970 112818 Chapter 3 Board Component Desc...

Page 70: ... Output 8 MODSELL BN6 QSFP2_RESETL_LS Output 9 RESETL BN7 QSFP2_MODPRSL_LS Output 27 MODPRSL BP6 QSFP2_INTL_LS Input 28 INTL BP7 QSFP2_LPMODE_LS Output 31 LPMODE U54 15 QSFP2_I2C_SDA BiDir 12 SDA U54 16 QSFP2_I2C_SCL Output 11 SCL QSFP3 J35 U1 bank 69 BM5 QSFP3_MODSKLL_LS Output 8 MODSELL BL6 QSFP3_RESETL_LS Output 9 RESETL BM7 QSFP3_MODPRSL_LS Output 27 MODPRSL BL7 QSFP3_INTL_LS Input 28 INTL BN4...

Page 71: ...tatus LEDs On power up or on reset the PHY is configured to operate in SGMII mode with PHY address 4 0 00011 The following table lists the FPGA U1 to U62 DP83867ISRGZ Ethernet PHY connections This table also shows the net names for the connections from the FPGA to the Ethernet PHY ENET_SGMII_IN correlates with the SGMII_TX ports in the FPGA design and ENET_SGMII_OUT correlates with the SGMII_RX po...

Page 72: ...n the Tri Mode Ethernet MAC LogiCORE IP Product Guide PG051 The TI DP83867ISRGZ data sheet is on the TI website I2C Bus Topology and Switches Figure 2 callout 25 26 The VCU128 evaluation board I2C bus implementation consists of I2C bus I2C0 The FPGA U1 HP bank 67 VCCO VCC1V8 and system controller U42 bank 501 are wired to I2C0 via level shifters I2C bus I2C0 is routed to a 1 to 4 channel TI PCA954...

Page 73: ... 501 U42 L S U58 L S U60 L S U49 TCA9548A SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 SD4 SC4 SD5 SC5 SD6 SC6 SD7 SC7 0X74 IIC EEPROM SDA SCL SI5328_SDA SCL NOT CONNECTED QSFP1_SI570_SDA SCL U53 TCA9548A SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 SD4 SC4 SD5 SC5 SD6 SC6 SD7 SC7 SDA SCL 0X76 U54 SDA SCL QSFP2_SI570_SDA SCL QSFP3_SI570_SDA SCL QSFP4_SI570_SDA SCL NOT CONNECTED FMCP_HSPC_IIC_SDA SCL NOT CONNECTED QSFP1_I2C...

Page 74: ...lock 3 0b1011101 0x5D U95 SI570 QSFP2 Si570 clock 4 0b1011101 0x5D U90 SI570 QSFP3 Si570 clock 5 0b1011101 0x5D U82 SI570 QSFP4 Si570 clock 6 0b1011101 0x5D U80 SI570 Not used 7 N A N A N A I2C0 Bus TCA9548 8 channel bus switch N A 0b1110101 0x76 U54 TCA9548A FMCP HSPC FMC Plus 0 0bXXXXXXX 0x J18 FMCP HSPC Not used 1 N A N A N A FPGA SYSMON 2 0b0110010 0x32 U1 BANK 65 Not used 3 N A N A N A QSFP1 ...

Page 75: ...5 GPIO_LED_5 DS6 GPIO_LED_4 DS7 GPIO_LED_5 DS8 GPIO_LED_6 DS9 GPIO_LED_7 DS10 FPGA INIT red green DS11 VCCINT 0 85V Mode DS12 VCCINT 0 72V Mode DS13 FPGA done DS14 VADJ_PG DS15 SYSTEM CTLR INIT red green DS16 SYSTEM CTLR error red DS17 SYSTEM CTLR status DS18 SYSTEM CTLR done DS19 ENET PHY link DS20 12V On EPHY P2 RT ENET LINK1000 EPHY P2 LFT ENET link activity Chapter 3 Board Component Descriptio...

Page 76: ...DS7 DS6 DS5 DS4 DS3 DS2 CPU_RESET GPIO pushbutton switch callout 29 CPU_RESET SW4 The following figure shows the GPIO circuits Figure 26 User GPIO X21972 112918 GPIO Connections to FPGA U1 The following table lists the GPIO connections to FPGA U1 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 76 Send Feedback ...

Page 77: ...1 BANK 67 BJ27 SMA_CLK_OUTPUT_N I O LVCMOS18 J13 1 Switches Figure 2 callouts 30 33 The VCU118 evaluation board includes a power on off slide switch and a configuration pushbutton switch FPGA Program_B SW4 active Low callout 30 Power on off slide switch SW5 callout 33 Power On Off Slide Switch SW5 Figure 2 callout 33 The VCU118 board power switch is SW5 Sliding the switch actuator from the off to ...

Page 78: ...B Pushbutton Switch Figure 2 callout 30 Switch SW2 grounds the XCVU37P FPGA U1 PROGRAM_B pin when pressed This action clears the FPGA configuration The FPGA_PROG_B signal is connected to XCVU37P FPGA U1 pin BB15 See the UltraScale Architecture Configuration User Guide UG570 for further configuration details The following figure shows SW2 Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 ...

Page 79: ...0 array The VCU128 board does not implement the high serial pin connector HSPCe extension FMC connectors use a 14 x 40 form factor populated with 560 pins The connector is keyed so that a mezzanine card when installed on the VCU128 evaluation board faces away from the board J18 FMC FMCP Connectors This section describes the J18 FMC FMCP connectors Samtec SEAF series 1 27 mm 0 050 in pitch Mates wi...

Page 80: ...tor at J18 implements a subset of the full FMCP connectivity 68 single ended or 34 differential user defined pairs full LA bus LA 00 33 24 transceiver differential pairs 6 transceiver differential clocks 2 differential clocks 239 ground and 14 power connections Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 80 Send Feedback ...

Page 81: ...P7_M2C_N LVDS AV52 A15 FMCP_HSPC_DP4_M2C_N LVDS AY52 B16 FMCP_HSPC_DP6_M2C_P LVDS AW49 A18 FMCP_HSPC_DP5_M2C_P LVDS AW53 B17 FMCP_HSPC_DP6_M2C_N LVDS AW50 A19 FMCP_HSPC_DP5_M2C_N LVDS AW54 B20 FMCP_HSPC_GBTCLK1_M2C_ P LVDS AR40 A22 FMCP_HSPC_DP1_C2M_P LVDS BC44 B21 FMCP_HSPC_GBTCLK1_M2C_ N LVDS AR41 A23 FMCP_HSPC_DP1_C2M_N LVDS BC45 B24 FMCP_HSPC_DP9_C2M_P LVDS AT46 A26 FMCP_HSPC_DP2_C2M_P LVDS BB...

Page 82: ... D14 FMCP_HSPC_LA09_P LVDS E26 C18 FMCP_HSPC_LA14_P LVDS C23 D15 FMCP_HSPC_LA09_N LVDS D26 C19 FMCP_HSPC_LA14_N LVDS B22 D17 FMCP_HSPC_LA13_P LVDS A25 C22 FMCP_HSPC_LA18_CC_P LVDS E19 D18 FMCP_HSPC_LA13_N LVDS A24 C23 FMCP_HSPC_LA18_CC_N LVDS E18 D20 FMCP_HSPC_LA17_CC_P LVDS F18 C26 FMCP_HSPC_LA27_P LVDS E21 D21 FMCP_HSPC_LA17_CC_N LVDS E17 C27 FMCP_HSPC_LA27_N LVDS D21 D23 FMCP_HSPC_LA23_P LVDS B...

Page 83: ...LA16_P LVDS K24 H16 FMCP_HSPC_LA11_P LVDS B26 G19 FMCP_HSPC_LA16_N LVDS K23 H17 FMCP_HSPC_LA11_N LVDS B25 G21 FMCP_HSPC_LA20_P LVDS A21 H19 FMCP_HSPC_LA15_P LVDS J26 G22 FMCP_HSPC_LA20_N LVDS A20 H20 FMCP_HSPC_LA15_N LVDS J25 G24 FMCP_HSPC_LA22_P LVDS B16 H22 FMCP_HSPC_LA19_P LVDS B18 G25 FMCP_HSPC_LA22_N LVDS A16 H23 FMCP_HSPC_LA19_N LVDS B17 G27 FMCP_HSPC_LA25_P LVDS D20 H25 FMCP_HSPC_LA21_P LVD...

Page 84: ... FMCP_HSPC_SYNC_C2M_P LVDS D25 M15 FMCP_HSPC_DP20_M2C_N LVDS AG54 L17 FMCP_HSPC_SYNC_C2M_N LVDS D24 M18 FMCP_HSPC_DP14_C2M_P LVDS AM46 L20 FMCP_HSPC_REFCLK_C2M_ P LVDS H24 M19 FMCP_HSPC_DP14_C2M_N LVDS AM47 L21 FMCP_HSPC_REFCLK_C2M_ N LVDS H23 M22 FMCP_HSPC_DP15_C2M_P LVDS AL44 L24 FMCP_HSPC_REFCLK_M2C_ P LVDS G26 M23 FMCP_HSPC_DP15_C2M_N LVDS AL45 L25 FMCP_HSPC_REFCLK_M2C_ N LVDS G25 M26 FMCP_HSP...

Page 85: ...M2C_ P LVDS AG40 Y22 FMCP_HSPC_DP15_M2C_P LVDS AL53 Z21 FMCP_HSPC_GBTCLK5_M2C_ N LVDS AG41 Y23 FMCP_HSPC_DP15_M2C_N LVDS AL54 Z24 FMCP_HSPC_DP10_C2M_P LVDS AR48 Y26 FMCP_HSPC_DP11_C2M_P LVDS AR44 Z25 FMCP_HSPC_DP10_C2M_N LVDS AR49 Y27 FMCP_HSPC_DP11_C2M_N LVDS AR45 Z28 FMCP_HSPC_DP12_C2M_P LVDS AP46 Y30 FMCP_HSPC_DP13_C2M_P LVDS AN44 Z29 FMCP_HSPC_DP12_C2M_N LVDS AP47 Y31 FMCP_HSPC_DP13_C2M_N LVDS...

Page 86: ...0A ISL91302 C UTIL_1V35 1 35V 10A ISL91302B A B D SYS_1V0 1 0V 2A ISL91302B C VCCAUX_HBM 2 5V 1 5A ISL80019 VCCHBM 1 2V 25A ISL68301 ISL99227B MGTAVTT 1 2V 20A ISL68301 ISL99227B VCCINT 0 85V 125A ISL68127 ISL919227 5 VCCBRAM 0 85V 30A ISL68127 ISL919227 1 Current Shunt Current Shunt Current Shunt Current Shunt 252W PCIe brick option Wattage calculations based on XPE requirements plus 25 overhead ...

Page 87: ... QDR4_VDDQ PH_A B ISL91302BIKZ TR5815 U44 1 2 5 6 0x62 NA NA 59 UTIL_1V30 PH_C D ISL91302BIKZ TR5815 U44 1 3 4 5 6 0x62 NA NA 60 RLD3_VDDQ PH_A B D ISL91302BIKZ TR5816 U67 1 2 7 10 0x64 NA NA 60 DDR4_VDDQ PH_C ISL91302BIKZ TR5816 U67 1 2 2 5 3 0x64 NA NA 61 UTIL_1V35 PH_A B D ISL91302BIKZ TR5817 U68 1 35 6 5 10 0x61 NA NA 61 SYS_1V0 PH_C ISL91302BIKZ TR5817 U68 1 1 75 2 0x61 NA NA 62 UTIL_3V3 ISL6...

Page 88: ...ough either the VCU128 system controller or the Intersil PowerNavigator software GUI The VCU128 system controller is a simple and convenient way to monitor the voltage and current values for the power rails listed in the following table The Intersil programmable power controllers listed in the table can also be accessed through the 2x3 male pin header J1 Using this connector requires the Intersil ...

Page 89: ...D ISL91302BIKZ TR5817 U68 1 35 6 5 10 0x61 NA NA 61 SYS_1V0 PH_C ISL91302BIKZ TR5817 U68 1 1 75 2 0x61 NA NA 62 UTIL_3V3 ISL68301IRAZ TR5826 U3 3 3 30 0x6A NA NA 62 UTIL_5V0 ISL68301IRAZ TR5825 U12 5 20 0x6B NA NA Non I2C Regulators 63 VCCAUX_HBM SL80019FRZ T7A U29 2 5 1 5 NA U79 0x4D 65 VCC_3V3 ISL85415FRZ T7A U25 3 3 20 NA NA NA 33 DDR4_VTERM_0V6 TPS51200DR U71 0 6 3 NA NA NA 33 RLD3_VTERM_0V6 T...

Page 90: ...includes a VCU128 System Controller Tutorial XTP534 and the VCU128 Software Install and Board Setup Tutorial XTP535 A summary of the steps is as follows 1 Ensure the Silicon Labs VCP USB UART drivers are installed on the host PC See the Silicon Labs CP210x USB to UART Installation Guide UG1033 2 Download the SCUI host PC application 3 Connect the micro B USB cable between the VCU128 board USB UART...

Page 91: ...able 2 mm keyed flat cable header J4 Each configuration interface corresponds to one or more configuration modes and bus widths as listed in the following table The mode switches M2 M1 and M0 are on 4 pole DIP SW1 positions 2 3 and 4 respectively The FPGA default mode setting M 2 0 001 selecting the master SPI configuration mode Table 34 Board FPGA Configuration Modes Configuration Mode SW16 DIP S...

Page 92: ...figuring the FPGA DIP switch SW1 also includes a system controller enable switch in position 1 See the UltraScale Architecture Configuration User Guide UG570 for further details on configuration modes Chapter 3 Board Component Descriptions UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 92 Send Feedback ...

Page 93: ...J18 defined by the VITA 57 4 FMC specification For a description of how the VCU128 evaluation board implements the FMCP specification see FPGA Mezzanine Card Interface Figure 32 FMCP Connector Pinouts X21978 112818 Appendix A VITA 57 4 FMCP Connector Pinouts UG1302 v1 1 April 21 2021 www xilinx com VCU128 Board User Guide 93 Send Feedback ...

Page 94: ...place the net names with the net names in the user RTL See the Vivado Design Suite User Guide Using Constraints UG903 for more information The FMCP connector J18 HSCP is connected to 1 8V nominal VADJ banks 70 and 71 Because different FMC cards implement different circuitry the FMC bank I O standards must be uniquely defined by each customer IMPORTANT See VCU128 board documentation for the XDC fil...

Page 95: ...ective CE Standards EN standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the International Electrotechnical Commission IEC Electromagnetic Compatibility EN 55022 2010 Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024 2010 Information Technology Equipment Immunit...

Page 96: ... life Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end of life If you have purchased Xilinx branded electrical or electronic products in the EU and are intending to discard these products at the end of thei...

Page 97: ...orials On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concepts and address frequently asked questions To access the Design Hubs In DocNav click the Design Hubs View tab On the Xilinx website see the Design Hubs page No...

Page 98: ...lock for PCI Express LogiCORE IP Product Guide PG156 9 Tri Mode Ethernet MAC LogiCORE IP Product Guide PG051 10 AXI UART Lite LogiCORE IP Product Guide PG142 11 Vivado Design Suite User Guide Using Constraints UG903 12 UltraScale Architecture PCB Design User Guide UG583 13 Silicon Labs CP210x USB to UART Installation Guide UG1033 14 VCU128 System Controller Tutorial XTP534 15 VCU128 Software Insta...

Page 99: ... VITA 57 4 specification is backwards compatible in that a VITA 57 4 carrier card can still support a VITA 57 FMC 29 Intersil Corporation a wholly owned subsidiary of Renesas Electronics Corporation The Intersil PowerNavigator software is available at https www intersil com en products power management zilker labs digital power powernavigator html The Intersil USB to PMBUS ZLUSBEVAL3Z Dongle is av...

Page 100: ...ch can be viewed at https www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Term...

Page 101: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Xilinx EK U1 VCU128 G EK U1 VCU128 G J EK U1 VCU128 ES1 G J EK U1 VCU128 ES1 G ...

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