Xilinx ChipScope Pro, User Manual

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ChipScope Pro Software and Cores User Guide www.xilinx.com 5
UG029 (v14.3) October 16, 2012
Chapter 1
Introduction
ChipScope Pro Tools Overview
As the density of FPGA devices increases, so does the impracticality of attaching test
equipment probes to these devices under test. The ChipScope™ Pro tools integrate key
logic analyzer and other test and measurement hardware components with the target
design inside the supported Xilinx® FPGA devices listed in the ISE® Design Suite Product
Table
[See Reference 16, p. 225] . The tools communicate with these components and
provide the designer with a robust logic analyzer solution.
The ChipScope Pro Serial I/O Toolkit provides features and capabilities specific to the
exploration and debug of designs that use the high-speed serial transceiver I/O capability
of FPGAs. The IBERT (internal bit error ratio tester) core and related software provides
access to the high-speed serial transceivers and perform bit error ratio analysis on channels
composed of these transceivers. In this document, the transceivers are called MGTs (multi-
gigabit transceivers). The IBERT core supports the high-speed serial transceivers found in
the Xilinx Virtex®-7, Kintex™-7, Virtex-6, Spartan®-6, and Virtex-5 FPGA devices listed in
the ISE Design Suite Product Table
[See Reference 16, p. 225] .
ChipScope Pro Tools Description
The following table gives a brief description of the various ChipScope Pro tools and cores.
Table 1-1: ChipScope Pro Tools Description
Tool Description
Xilinx CORE
Generator™ tool
Provides core generation capability for the ICON (integrated
controller), ILA (integrated logic analyzer), VIO, (virtual
input/output), and ATC2 (Agilent trace core) cores targeting all
supported FPGA device families. Also provides core generation
capability for the IBERT v2.0 core targeting the
Virtex-7, Kintex-7,
Virtex-6, Spartan-6, and Virtex-5 FPGA families. The Xilinx CORE
Generator tool is part of the Xilinx ISE Design Suite tool installation.
IBERT Core
Generator
Provides full design generation capability for the IBERT v1.0 core
targeting the Virtex-5 devices. You select the MGTs and parameters
governing the design, and the CORE Generator tool uses the ISE
design suite to produce a configuration file.
Core Inserter
Automatically inserts the ICON, ILA, and ATC2 cores into your
synthesized design.