Xilinx CAN FD v2.0, Product Manual

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CAN FD v2.0 50
PG223 December 5, 2018 www.xilinx.com
Chapter 2: Product Specification
CAN FD RX Message Space (Sequential/FIFO Buffers-RX FIFO-0)
Register Descriptions
25:24 ET Status N/A
Event Type.
• 11 -> Transmitted.
• 01 -> Transmitted in spite of cancellation request or DAR
mode transmissions.
• 00 -> Reserved.
• 10 -> Reserved.
23:16 MM Status N/A
Message Marker.
Written by CPU during TX Buffer configuration. Copied into
Tx Event FIFO element for identification of TX message
status.
15:0 Timestamp Status N/A
Timestamp captured after SOF bit. This is written by the core
for status purpose for successfully transmitted message.
Table 2-37: CAN FD RX Message Space (Sequential/FIFO Buffers - RX FIFO-0)
Start
Address
Name Access Description Notes
64 Message Deep Sequential (FIFO) Buffer Space
0x2100 RB0-ID Read Only
RB ID Register
RB0 Message space inside
memory mapped RX block
RAM.
Only required DW locations
needs to be read as per FDF
and DLC field for a given
message.
IMPORTANT:
Ensure no
unintended writes are done
from Host interface to RX
block RAM message space
(core does not block writes to
RX block RAM message
space).
0x2104 RB0-DLC Read Only RB DLC Register
0x2108 RB0-DW0 Read Only RB DW0 Register
Table 2-36: TXE FIFO TB DLC Register (Cont’d)
Bits Name
Control/
Status
Default
Value
Description
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