CAN FD v2.0
33
PG223 December 5, 2018
Chapter 2:
Product Specification
IMPORTANT:
Performing unnecessary cancellation of TX buffers might reduce core throughput on the
CAN bus. Ensure that buffer cancellation is requested only when it is required.
Interrupt Enable TX Buffer Cancellation Served/Cleared (Address
0x009C)
TX Event FIFO Status Register (Address 0x00A0)
Table 2-21:
Interrupt Enable TX Buffer Cancellation Request Served/Cleared Register
Bits
Name
Access
Default
Value
Description
31:8
ECRS31/ECRS8
R/W
0
Note:
These bits exist based on the number of TX buffers.
7
ECRS7
R/W
0
TX Buffer_0 Transmission Served/Cleared Interrupt Enable
• 1 = Enables setting TXCRS bit in the ISR when CR0 bit in
TCS register clears.
• 0 = TXCRS bit in the ISR does not set if CR0 bit in TCS
register clears.
6
ECRS6
5
ECRS5
4
ECRS4
3
ECRS3
2
ECRS2
1
ECRS1
0
ECRS0
Table 2-22:
TX Event FIFO Status Register
Bits
Name
Access Default
Value
Description
31:14
Reserved
-
0
Reserved
13:8
TXE_FL[5:0]
R
0
Fill Level (0-32)
Number of stored message in TX Event FIFO
starting from RI index given in this register.
For example, if FL = 0x5 and RI = 0x3 then TX Event
FIFO has five messages starting from Read Index 3
(Start address 0x2018).
FL is maintained if CEN bit is cleared.
FL gets reset to 0 if soft or hard reset is asserted.
7
TXE_IRI
W
0
Increment Read Index by 1
With each Host writes setting this bit as 1, core
increments Read index
(RI field) by 1 and update fill level (that is,
decrement by 1).
If FILL level is 0, setting this bit has no effect. The
FILL level might remain unchanged when IRI is
written if core is just finishing a successful
transmission and incrementing internal write index.
This bit always read as 0.
