DPU IP Product Guide
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PG338 (v1.2) March 26, 2019
Chapter 6: Example Design
Introduction
The Xilinx® DPU targeted reference design (TRD) provides instructions on how to use DPU with a Xilinx
SoC platform to build and run deep neural network applications. The TRD uses the Vivado® IP
integrator flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design.
The Zynq® Ult™ MPSoC platform is used to create this TRD. It can also be used for a Zynq-
7000 SoC platform with the same flow.
This appendix describes the architecture of the reference design and provides a functional description
of its components. It is organized as follows:
•
DPU TRD Overview
provides a high-level overview of the Zynq Ult MPSoC device
architecture, the reference design architecture, and a summary of key features.
•
Hardware Design Flow
gives
an overview of how to use Xilinx Vivado Design Suite to generate
the reference hardware design.
•
Software Design Flow
describes
the design flow of project creation in the PetaLinux
environment.
•
Demo Execution
describes how to run the application created by the TRD.
DPU TRD Overview
The TRD creates an image classification application running a popular deep neural network model,
Resnet50, on a Xilinx Ult MPSoC device. The overall functionality of the TRD is partitioned
between the Processing System (PS) and Programmable Logic (PL), where DPU resides for optimal
performance.
The following figure shows the TRD block diagram. The host communicates with the ZCU102 board
through Ethernet or UART port. The input images for a TRD are stored in an SD card. When the TRD is
running, the input data is loaded into DDR memory, then DPU reads the data from the DDR memory
and writes the results back to DDR memory. The result displays on the host screen from the APU
through Ethernet or UART port.
