7 Series FPGAs Configurable Logic Block
User Guide
UG474 (v1.8) September 27, 2016
Page 1: ...7 Series FPGAs Configurable Logic Block User Guide UG474 v1 8 September 27 2016...
Page 2: ...FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE SAFETY APPLICATION UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262...
Page 3: ...programmable in Control Signals page 22 Added Primitive column to Table 2 3 and removed footnotes Renamed or made minor revisions to Figure 2 6 through Figure 2 14 Revised sections Clock WCLK page 49...
Page 4: ...7 Series FPGAs CLB User Guide www xilinx com UG474 v1 8 September 27 2016...
Page 5: ...Look Up Table LUT 21 Storage Elements 21 Distributed RAM Available in SLICEM Only 23 Shift Registers Available in SLICEM Only 34 Multiplexers 39 Carry Logic 43 Chapter 3 Design Entry Design Checklist...
Page 6: ...iming Model and Parameters Available in SLICEM Only 63 CLB Slice SRL Shift Register Timing Model and Parameters Available in SLICEM Only 66 Chapter 6 Advanced Topics Using the Latch Function as Logic...
Page 7: ...e number and distribution of the available flip flops and the availability of the very efficient shift registers This guide describes these and other features of the CLB in detail This 7 Series FPGAs...
Page 8: ...FPGA data sheet Chapter 6 Advanced Topics discusses advanced features of the 7 series CLB Additional Support Resources To find additional documentation see the Xilinx website at http www xilinx com su...
Page 9: ...s to the general routing matrix shown in Figure 1 1 A CLB element contains a pair of slices The LUTs in 7 series FPGAs can be configured as either a 6 input LUT with one output or as two 5 input LUTs...
Page 10: ...nd flexibility relative to the Virtex 6 FPGA family improving the quality of automatic place and route results Device Resources The CLB resources are scalable across all the 7 series families providin...
Page 11: ...2 1 800 800 10 400 200 100 20 800 7A25T 3 650 2 400 1 250 14 600 313 156 29 200 7A35T 5 200 2 3 600 1 600 20 800 400 200 41 600 7A50T 8 150 5 750 2 400 32 600 600 300 65 200 7A75T 11 800 2 8 232 3 56...
Page 12: ...d RAM or SRLs 2 Number of slices corresponding to the number of LUTs and flip flops supported in the device Table 1 3 Kintex 7 FPGA CLB Resources Cont d Device Slices 1 SLICEL SLICEM 6 input LUTs Dist...
Page 13: ...evice The ASMBL architecture provides maximum flexibility with CLBs on both sides of most I Os The best approach is to let the tools choose the I O locations based on the FPGA requirements Results can...
Page 14: ...14 www xilinx com 7 Series FPGAs CLB User Guide UG474 v1 8 September 27 2016 Chapter 1 Overview Send Feedback...
Page 15: ...s Available in SLICEM Only SLICEM ability to use LUTs as shift registers Multiplexers Dedicated gates for combining LUTs into wide functions Carry Logic Dedicated gates and cascading to implement effi...
Page 16: ...interposer layer to create a single FPGA with more than ten thousand inter SLR connections See Chapter 6 Advanced Topics for additional information CLB Slices A CLB element contains a pair of slices a...
Page 17: ...bottom Figure 2 2 shows four CLBs located in the bottom left corner of the die CLB Slice Configurations Table 2 1 summarizes the logic resources in one CLB Each SLICEM LUT can be configured as a look...
Page 18: ...by all slices to provide logic arithmetic and ROM functions In addition some slices support two additional functions storing data using distributed RAM and shifting data with 32 bit registers Slices t...
Page 19: ...MUX A AQ AMUX Reset Type D FF LAT INIT1 INIT0 SRHI SRLO SR CE CK FF LAT INIT1 INIT0 SRHI SRLO FF LAT INIT1 INIT0 SRHI SRLO FF LAT INIT1 INIT0 SRHI SRLO D SR CE CK D SR CE CK D SR Q CE CK CIN 0 1 WEN W...
Page 20: ...MUX A AQ AMUX Reset Type D FF LAT INIT1 INIT0 SRHI SRLO SR CE CK FF LAT INIT1 INIT0 SRHI SRLO FF LAT INIT1 INIT0 SRHI SRLO FF LAT INIT1 INIT0 SRHI SRLO D SR CE CK D SR CE CK D SR Q CE CK CIN 0 1 Sync...
Page 21: ...ry logic chain from an O5 output Enter the select line of the carry logic multiplexer from O6 output Feed the D input of the storage element Go to F7AMUX F7BMUX wide multiplexers from O6 output In add...
Page 22: ...n the clock signal is automatically absorbed The CE and SR signals are active High These initialization options are available for storage elements SRLOW Synchronous or asynchronous Reset when CLB SR s...
Page 23: ...IGH attribute sets INIT1 7 series devices can set INIT0 and INIT1 independent of SRHIGH and SRLOW The configuration options for the set and reset functionality of a register or the four storage elemen...
Page 24: ...ide for details of available distributed RAM primitives Distributed RAM configurations include Single port Common address port for synchronous writes and asynchronous reads Read and write addresses sh...
Page 25: ...ys physically driven by the inputs to the D LUT using D 6 1 The read ports are independent for each of the four LUTs Therefore the D LUT is always effectively single port even if DPRAM64 is selected a...
Page 26: ...UG474_c2_06_070914 DI1 DOD 0 DOC 0 DOD 1 DOC 1 DOB 0 DOB 1 DOA 0 DOA 1 DI2 DID 1 DID 0 ADDRD 4 0 ADDRC 4 0 ADDRB 4 0 ADDRA 4 0 WCLK WED CLK WE 5 5 DPRAM32 RAM32M A 6 1 WA 6 1 CLK WE O6 O5 DI1 DI2 5 5...
Page 27: ...RAM RAM32M UG474_c2_06_070914 DI1 O 2 O 1 O 4 O 3 O 6 O 5 DI2 unused unused WADDR 5 1 WADDR 6 1 RADDR 5 1 RADDR 6 1 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 WCLK WED CLK WE 5 5 DPRAM32 RAM32M A 6 1 W...
Page 28: ...a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to a 64 x 2 bit dual port distributed RAM X Ref Target Figure 2 8 Fi...
Page 29: ...4M UG474_c2_09_070914 DI1 DID ADDRD ADDRC ADDRB ADDRA WCLK WE CLK WE DPRAM64 RAM64M A 6 1 WA 6 1 CLK WE O6 DI1 DPRAM64 A 6 1 WA 6 1 CLK WE O6 DI1 B 6 1 C 6 1 D 6 1 DI A 6 1 DPRAM64 A 6 1 WA 6 1 CLK WE...
Page 30: ...tives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 128 x 2 bit single port distributed RAM X Ref Ta...
Page 31: ...n SLICEM Only X Ref Target Figure 2 12 Figure 2 12 128 X 1 Single Port Distributed RAM RAM128X1S UG474_c2_11_101210 DI1 DI A6 CX D A 6 0 WCLK WE CLK WE CE 5 0 5 0 7 SPRAM64 RAM128X1S A 6 1 WA 7 1 CLK...
Page 32: ...ort Distributed RAM RAM128X1D UG474_c2_12_101210 DI1 D DI AX A 6 0 WCLK DPRA 6 0 WE CLK WE 7 DPRAM64 RAM128X1D A 6 1 WA 7 1 CLK WE O6 DI1 6 7 DPRAM64 A 6 1 WA 7 1 CLK WE O6 Registered Output F7BMUX Op...
Page 33: ...o form larger distributed RAM configurations within a CLB or between slices X Ref Target Figure 2 14 Figure 2 14 256 X 1 Single Port Distributed RAM RAM256X1S UG474_c2_13_101210 DI1 D A 7 0 WCLK WE CL...
Page 34: ...utput The data input has a setup to clock timing specification Read Only Memory ROM Each function generator in both SLICEMs and SLICELs can implement a 64 x 1 bit ROM Three configurations are availabl...
Page 35: ...to as Q on the primitive by varying the address This capability is useful in creating smaller shift registers less than 32 bits For example when building a 13 bit shift register set the address to th...
Page 36: ...o the first bit of the next without using the LUT O6 output Longer shift registers can be built with dynamic access to any bit in the chain The shift register chaining and the F7AMUX F7BMUX and F8MUX...
Page 37: ...A 6 2 CLK WE O6 MC31 MC31 DI1 5 SRL32 A 6 2 CLK WE O6 Registered Output Output Q F7AMUX Optional D Q A5 AX AQ SHIFTOUT Q63 MC31 X Ref Target Figure 2 19 Figure 2 19 96 Bit Shift Register Configuration...
Page 38: ...tion has these characteristics Operates on a single clock edge Enabled by an active High clock enable The input D is loaded into the first bit of the shift register Each bit is also shifted to the nex...
Page 39: ...1 to 32 bits in one LUT The shift register length is N 1 where N is the input address 0 31 The Q output changes synchronously with each shift operation The previous bit is shifted to the next position...
Page 40: ...ements Designing Large Multiplexers 4 1 Multiplexer Each LUT can be configured into a 4 1 MUX The 4 1 MUX can be implemented with a flip flop in the same slice Up to four 4 1 MUXes can be implemented...
Page 41: ...a slice as shown in Figure 2 22 X Ref Target Figure 2 22 Figure 2 22 Two 8 1 Multiplexers in a Slice UG474_c2_21_101210 D 6 1 C 6 1 CX B 6 1 A 6 1 AX SELF7 1 CLK CLK SELF7 2 SEL D 1 0 DATA D 3 0 Inpu...
Page 42: ...te multiplexers wider than 16 1 across more than one SLICEM However there are no direct connections between slices to form these wide multiplexers X Ref Target Figure 2 23 Figure 2 23 16 1 Multiplexer...
Page 43: ...ected carry bits The dedicated carry path and carry multiplexer MUXCY can also be used to cascade function generators for implementing wide logic functions Figure 2 24 illustrates the carry chain with...
Page 44: ...or add 1 for subtract AX input for the dynamic first carry bit CIN Cascade slices to form a longer carry chain Outputs O outputs O0 to O3 Contain the sum of the addition subtraction CO outputs CO0 to...
Page 45: ...iting factor and consider using alternative resources such as moving registers to SRLs or distributed RAM or distributed RAM to block RAM or carry logic to DSP slices When migrating a design from anot...
Page 46: ...l does not infer a desired special CLB resource such as the wide multiplexers distributed RAM or SRL feature Primitives This section provides an overview of the most commonly used CLB primitives For i...
Page 47: ...ltipliers Figure 3 2 shows the CARRY4 primitive Synthesis tools generally infer this logic from arithmetic HDL code automatically connecting this function properly Port Signals Sum Outputs O 3 0 The s...
Page 48: ...are shown in Table 3 2 Three primitives are single port RAM three primitives are dual port RAM and two primitives are quad port RAM The input and output data are one bit wide with the exception of th...
Page 49: ...to memory cells An active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs Address A 0 DPRA 0 and ADDRA 0 ADDRD 0 The address i...
Page 50: ...ock signal can be active at the negative or positive edge without requiring other logic resources The default is positive clock edge Data In D The data input provides new data one bit to be shifted in...
Page 51: ...p Clock C Either the rising edge or the falling edge of the clock is used to capture data and toggle the output The data and clock enable input pins have setup times referenced to the chosen edge of t...
Page 52: ...ous Clear CLR When CLR is High all other inputs are overridden and the data output Q is driven Low This signal is available in the FDCE component The FDCE flip flop is also cleared by default on power...
Page 53: ...tributed RAM is more efficient in terms of resources performance and power For depths greater than 64 bits but less than or equal to 128 bits the decision on the best resource to use depends on these...
Page 54: ...and F8MUX Figure 4 2 illustrates a 72 bit shift register Only the last SRLC32E primitive needs to have its address inputs tied to 0b00111 Alternatively shift register length can be limited to 71 bits...
Page 55: ...application A small arithmetic function can be faster and lower power using the CLB carry logic rather than using an entire DSP48E1 slice When the DSP48E1 slices are fully utilized the CLB slices and...
Page 56: ...56 www xilinx com 7 Series FPGAs CLB User Guide UG474 v1 8 September 27 2016 Chapter 4 Applications Send Feedback...
Page 57: ...CLB General Slice Timing Model and Parameters page 58 CLB Slice Multiplexer Timing Model and Parameters page 60 CLB Slice Carry Chain Timing Model and Parameters page 61 CLB Slice Distributed RAM Timi...
Page 58: ...hs described in this section are shown X Ref Target Figure 5 1 Figure 5 1 Simplified 7 Series FPGA Slice UG474_c5_01_101210 LUT O6 O5 6 D FF LAT D CE CLK SR Q F7BMUX F8MUX DMUX DQ D Inputs LUT O6 O5 6...
Page 59: ...the slice sequential elements configured as a latch TSHCKO FF Clock CLK to AMUX BMUX CMUX DMUX outputs Time after the clock that data is stable at the AMUX BMUX CMUX DMUX outputs through the slice fl...
Page 60: ...CLB Slice Multiplexer Timing Model and Parameters Figure 2 22 page 41 and Figure 2 23 page 42 illustrate the wide multiplexers in a 7 series FPGA slice Slice Multiplexer Timing Parameters Table 5 2 sh...
Page 61: ...the C LUT inputs of the slice through the F7BMUX multiplexer to the CMUX output of the slice Table 5 2 Slice Multiplexer Timing Parameters Cont d Parameter Function Description Table 5 3 Slice Carry C...
Page 62: ...lock event 1 TCINA TCINB TCINC TCIND CIN input to AMUX BMUX CMUX DMUX outputs Propagation delay from the CIN input of the slice to AMUX BMUX CMUX DMUX outputs of the slice using XOR sum Setup and Hold...
Page 63: ...s FPGA slice Some elements of the slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown X Ref Target Figure 5 4 Figure 5 4 Simplified 7 Serie...
Page 64: ...MUX BMUX CMUX DMUX outputs of the slice Setup and Hold Times for a Slice LUT Configured as RAM Distributed RAM 1 TDS TDH TDS_LRAM TDH_LRAM AI BI CI DI configured as data inputs DI1 2 Time before after...
Page 65: ...event 1 the DATA becomes valid 1 at the DI input of the RAM and is reflected on the A B C D outputs at time TSHCKO after clock event 1 This is also applicable to the AMUX BMUX CMUX DMUX and COUT outp...
Page 66: ...ries FPGA slice Some elements of the slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown X Ref Target Figure 5 6 Figure 5 6 Simplifie...
Page 67: ...e operation that the data written to the SRL is stable on the DMUX output via MC31 output Setup and Hold Times for a Slice LUT Configured as an SRL 2 TCECK TCKCE TCECK_SHFREG TCKCESHFREG CE input CE T...
Page 68: ...address 0 is specified at clock event 1 the data on the DI input is reflected at A B C D output because it is written to register 0 Clock Event 2 Shift In At time TDS before clock event 2 the data be...
Page 69: ...is example this was the first data shifted in and it is reflected on the A B C D output after a delay of length TILO Clock Event 32 MSB Most Significant Bit Changes At time TREG after clock event 32 t...
Page 70: ...70 www xilinx com 7 Series FPGAs CLB User Guide UG474 v1 8 September 27 2016 Chapter 5 Timing Send Feedback...
Page 71: ...2B1L combines the latch data input the inverted input on the gate DI with the asynchronous clear input SRI The OR2L combines the latch data input with an asynchronous preset Generally the latch data i...
Page 72: ...designers Knowledge of the interconnect details can be used to guide design techniques but is not necessary for efficient FPGA design Only selected types of interconnect are under user control These...
Page 73: ...minimizes any additional loads on the inputs to the source function Replicating logic in multiple slices gives the software more flexibility to place the sources independently Floorplanning is the pro...
Page 74: ...iques timing constraints or options to automatically find the best implementation Floorplanning for these devices can use the same graphical tools For more information on devices using SSI technology...
