microDXP Technical Reference Manual
Version 3.15
October 7, 2019
14
1.3.4 Pipeline Clock Speed Choice
The pipeline clock runs by default at 40 MHz. An 80 MHz hardware option is also
available. Simply put, the clock speed determines the scale of available peaking times and
the timing resolution. A faster clock produces shorter peaking times, better pileup rejection
and a higher output count rate, but a faster clock also results in higher power consumption.
The following table illustrates these points:
Clock Speed
Sampling Period
Max OCR
Power Consumption
40 MHz (default)
25 ns
1,000,000 cps
750 mW
80 MHz (high-speed)
12.5 ns
2,000,000 cps
800 mW
Table 1-3: Data pipeline (ADC and FiPPI) clock speed options.
1.3.5 Gain and Calibration Options
The microDXP by default includes computer-controlled variable analog gain. The variable
gain circuit provides 25.5 dB of digitally-controlled analog gain in 16 discrete steps in
addition to the digital fine gain trim. This allows the microDXP to be optimized for a wide
range of x-ray energies and a wide variety of detectors. The microDXP can be further
optimized via a custom input-attenuation circuit, which also allows for customization of
the input impedance.
The microDXP can alternatively be built with fixed-gain, i.e. a user-selected analog gain
is implemented in the on-board circuitry. The gain tolerance will typically be at the one
percent level, and only digital scaling is used for energy calibration. The fixed-gain option
offers better performance in some cases, and somewhat lower power consumption.
The analog gain is further described in §3.2.2 and the digital gain is described in §3.4.3.
The gain architecture that is installed can be determined via software, as described in
§2.2.1.2. A separate document, the microDXP Gain Specification, contains all relevant info
with examples.
1.4 Firmware Options
The term firmware refers to code running on the PIC microcontroller, USB
microcontroller, DSP and the FPGA that comprises the Filter-Pulse-Pileup-Inspector, or
FiPPI. The PIC and/or USB microcontrollers handle communications. The digital signal
processor (DSP) manages high-level operations and calculations. The reconfigurable
digital shaping, triggering, and pileup-rejection algorithms are contained in a field-
programmable-gate-array (FPGA). Each complete configuration code is referred to as a
FiPPI (Filter Pulse Pileup Inspector). Firmware updates will be posted to the XIA website.
Please check the microDXP page at:
http://www.xia.com/microDXP.html
1.4.1 Preamplifier Type
Two standard firmware options are offered, corresponding to the two preamplifier types
that are commonly used: reset-type and RC-feedback. Please make sure to specify the
correct type at the time of your order so that the appropriate firmware is loaded.
In ProSpect, the preamplifier type corresponding to the loaded firmware is displayed in the
Detector tab of the Settings panel. The DSP code variant (DSP parameter CODEVAR) is
