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XS40 BOARD V1.4 USER MANUAL 

 

8

 

Testing Your XS40 Board 

Once your XS40 Board is installed and the jumpers are in their default configuration, you 
can test the board using the GUI-based GXSTEST utility as follows. 

You start GXSTEST by clicking on the 

 icon placed on the desktop during the 

XSTOOLS installation.  This brings up the window shown below. 

 

Next you select the parallel port that your XS40 Board is connected to from the Port 
pulldown list.  GXSTEST starts with parallel port LPT1 as the default, but you can also 
select LPT2 or LPT3 depending upon the configuration of your PC. 

After selecting the parallel port, you select the type of XS40 Board you are testing from the 
Board Type pulldown list.  Then click on the TEST button to start the testing procedure.  
GXSTEST will configure the FPGA  to perform a test procedure on your XS40 Board.  
After several seconds you will see a 

O

O

O

O

 displayed on the LED digit if the test completes 

successfully.  Otherwise an 

E

E

E

E

 will be displayed if the test fails.  A status window will also 

appear on your PC screen informing you of the success or failure of the test. 

If your XS40 Board fails the test, you will be shown a checklist of common causes for 
failure.  If none of these causes applies to your situation, then test the XS40 Board using 
another PC.  In our experience, 99.9% of all problems are due to the parallel port.  If you 
cannot get your board to pass the test even after taking these steps, then contact XESS 
Corp for further assistance. 

Programming Your XS40 Board Clock Oscillator 

The XS40/XSP Board has a 100 MHz programmable oscillator (a Dallas Semiconductor 
DS1075Z-100).  The 100 MHz master frequency can be divided by factors of 1, 2, ... up to 
2052 to get clock frequencies of 100 MHz, 50 MHz, ... down to 48.7 KHz, respectively.  
The divided frequency is sent to the rest of the XS40/XSP Board circuitry as a clock signal. 

The divisor is stored in non-volatile memory in the oscillator chip so it will resume 
operation at its programmed frequency whenever power is applied to the XS40/XSP 
Board.  You can store a particular divisor into the oscillator chip by using the GUI-based 
GXSSETCLK utility as follows. 

Summary of Contents for XStend XS40

Page 1: ...oard V1 4 XS40 XSP Board V1 4 XS40 XSP Board V1 4 User Manual User Manual User Manual User Manual How to install test and use your new XS40 or XSP Board 2608 Sweetgum Drive Apex NC 27502 Toll free 800...

Page 2: ...Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any mea...

Page 3: ...your XILINX Foundation software tools installed properly send an e mail message describing your problem to hotline xilinx com or check their web site at http support xilinx com Take notice The XS40 B...

Page 4: ...r package an XS40 or XSP Board note that your XSP Board will be labeled as an XS40 but the socket will contain a Xilinx Spartan FPGA with an XCS prefix a 6 cable with a 25 pin male connector on each e...

Page 5: ...a non conducting surface as shown in Figure 1 Then apply power to jack J9 of the XS40 Board from a 9V DC wall transformer with a 2 1 mm female center positive plug See Figure 2 for the location of jac...

Page 6: ...pins for the various XS40 Boards XS40 Board Type GND Pin 5V Pin 3 3V Pin XS40 005E V1 4 52 2 54 none XS40 005XL V1 4 52 2 54 XS40 010E V1 4 52 2 54 none XS40 010XL V1 4 52 2 54 XSP 010 V1 4 52 2 54 no...

Page 7: ...1 Connecting a VGA Monitor to Your XS40 Board You can display images on a VGA monitor by connecting it to the 15 pin J2 connector at the bottom of your XS40 Board see Figure 1 You will have to downloa...

Page 8: ...OM U7 On The shunt should be installed when the on board serial EEPROM U7 is being programmed J6 Off default The shunt should be removed during normal board use 1 2 ext default The shunt should be ins...

Page 9: ...be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test If your XS40 Board fails the test you will be shown a checklist of...

Page 10: ...ype pulldown list Next you enter a divisor between 1 and 2052 into the Divisor text box and then click on the SET button Then follow the sequence of instructions given by GXSSETCLK for moving shunts a...

Page 11: ...ownload your circuit each time you make changes to it You can download an FPGA design into your XS40 Board using the GXSLOAD utility as follows You start GXSLOAD by clicking on the icon placed on the...

Page 12: ...g on the Load button will begin sending the highlighted file to the XS40 Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA GXSLOAD wil...

Page 13: ...to store the bitstream in a serial EEPROM placed in socket U7 on your XS40 Board The EEPROM will configure the FPGA for operation as soon as power is applied The XILINX XC1700 is a series of serial EE...

Page 14: ...EPROM upon power on 1 Remove the downloading cable from connector J1 of the XS40 Board As an alternative you can use the command XSPORT 0 to make sure the upper two data bits of the parallel port are...

Page 15: ...he FPGA remains configured as an interface to the RAM You can also examine the contents of the RAM device by uploading it to the PC To upload data from an address range in the RAM type the upper and l...

Page 16: ...e some new intra system inputs and outputs created by the need for the microcontroller and the FPGA to cooperate In general the FPGA will be used mainly for low level functions where signal transition...

Page 17: ...like placing printf statements in your C language programs This is admittedly crude but will serve if you don t have access to a programmable stimulus generator or logic analyzer Figure 3 FPLD microc...

Page 18: ...igh Many of the I O pins of ports P1 and P3 of the microcontroller connect to the FPGA and can be used for general purpose I O between the microcontroller and the FPGA In addition to being general pur...

Page 19: ...atus input pins of the PC parallel port Pin 67 drives the vertical sync signal for a VGA monitor 69 P3 1 TXD PC S6 68 P3 4 T0 PS 2 CLK 62 P3 6 WRB WEB 27 P3 7 RDB These pins connect to some of the pin...

Page 20: ...P C _D 4 P C _D 3 P C _D 2 P C _D 1 R E D 0 G R E E N 0 B LU E 1 R E D 1 H S Y N C V S Y N C G R E E N 1 S 3 S 4 S 5 S 6 F P G A 7 S egm entLE D V G A In p u ts P C P a ra l l e l P o rt D a ta O u tp...

Page 21: ...XS40 BOARD V1 4 USER MANUAL 20...

Page 22: ...XS40 BOARD V1 4 USER MANUAL 21...

Page 23: ...xs40v1_4 sch 1 Mon Sep 6 13 53 50 1999...

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