Worldline Six VALINA, Integration Manual, Page: 21 / 24

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For development and repair purposes, the VALINA is equipped
with a JTAG/Debug port, underneath the TELECOM cover.
This port can be used to connect a PACIFIC Debug Interface
for debugging and logging purposes. This port can also be
used to connect a JTAG Interface for repair and reflash purposes.
The following interfaces are available on this port:
• JTAG-interface towards the ASIC
• 3.3V UART interface towards Core 1 (secured – UART_A3)
• 3.3V UART interface towards Core 2 (unsecured – UART_B3)
1
Figure 19: JTAG/DEBUG port
1
The JTAG/Debug port uses a spring-loaded connector with
2.54 mm pins.
Pinout for JTAG/DEBUG port – springport
Pin Description Pin Description
1
3.3V
11
TDO
2
GND
12
GND
3
TRSTn
13
3.3V
4
GND
14
12C_SCL
5
TDI
15
12C_SDA
6
GND
16
SRSTn
7
TMS
17
UART4_RXD
8
GND
18
UART4_TXD
9
TCK
19
UART5_RXD
10
GND
20
UART5_TXD
The JTAG/DEBUG Port is also available via a pinheader with
a pitch of 1.27 mm, which is available on prototypes and devel-
opment terminals.
Pinout for JTAG/Debug port – pinheader
Pin Description Pin Description
1
GND
7
SRSTn
2
TCK
8
3.3V
3
TDI
9
UART4_ RXD (debug)
4
TDO
10
UART4_TXD (debug)
5
TMS
11
UART5_ RXD (debug)
6
TRSTn
12
UART5_TXD (debug)
9 JTAG/DEBUG PORT