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WaveNet Link AX Installation and Operations Manual
2.5.2 Link AX Receiver
The receiver in theLink AX is a conventional dual conversion design with IF frequencies of
474.88 MHz and 70 MHz.
From the receive port of the duplexer, the low level input signal is passed through a low noise
preamplifier that provides 25 dB of gain. Following the preamplifier the signal is passed
through a 200 MHz wide bandpass filter to provide image rejection for the first mixer.
The signal is then mixed with the first LO to convert the signal to 474.88 MHz. Following further
amplification the signal is passed through a five pole, 20 MHz wide bandpass filter. This filter
provides image filtering for the second mixer, and also helps attenuate signals on the adjacent
receive channels. After filtering, the signal is further amplified and then passed through a
variable attenuator stage before it is applied to the second mixer.
The output of the second mixer is at 70 MHz. The 70 MHz IF stages provide additional gain
along with two sections of variable attenuation for the AGC function. The primary adjacent
channel filtering is also at 70 MHz where the signal is passed through a 12 MHz wide SAW filter.
The combination of filters provide a minimum of 47 dB of attenuation at the adjacent receive
channels (
±
10.24 MHz).
At the end of the 70 MHz IF chain the signal is fed into a quadrature demodulator. The carrier
recovery loop consists of a four quadrant multiplier that multiplies I and Q baseband signals
to create an error voltage. This error voltage is then amplified and fed back to the 70 MHz VCO.
This forms a phase locked loop that is locked to the received carrier frequency.
The 70 MHz output is also fed into a wide band logarithmic amplifier that provides a DC voltage
output proportional to the 70 MHz signal strength. The DC voltage is then integrated and fed
back to the variable attenuator stages to form an AGC control loop. This control loop keeps
the signal level at the input to the demodulator chip constant over the entire operating range
of the receiver.
Data recovery from the I baseband signal begins by passing the I signal through a slicer. The
output of the slicer is a digital signal that contains both data and clocking information. A clock
recovery circuit recovers receive timing information that is needed to clock the data through
the descrambler, and differential decoder.
This 8.448 Mb bit stream is then converted into ATM cells. The SYNC bytes and the inserted
zeros are stripped form the cells prior to their delivery to the ATM25 PHY. This method provides
worst case cell rate of 15645 cells per second (cps) and typical cell rates of approximately
19200 cps.
