PCM-MIO-A-1/Software Summary
v1.0
www.winsystems.com
Page 27
If the application requires all DAC channels to be configured to the same
output span, command value 8Xh supports this action with a single
instruction sequence. Likewise if all DAC channels are written with the
same data output, then command value 9Xh both pre-loads and presents
the value to all DAC channels with a single instruction sequence.
8.3
Registers
8.3.1 Register Definitions (WS16C48 Logic)
The PCM-MIO-A-1 and PCM-MIO-A-AD-1 use a Lattice MachXO2 FPGA with
WINSYSTEMS WS16C48 ASIC compatible programmed logic. This provides
48 lines of digital I/O. There are 17 unique registers within the WS16C48
Write
High Byte data
to BASE +9.
Write
CMD 00110000
to BASE +10.
Move data to B1 Code
7. To pre-load Data Output for Channel 1:
Write
Low Byte data
to BASE +8.
Write
High Byte data
to BASE +9.
Write
CMD 00110010
to BASE +10.
Move data to B1 Code
8. To pre-load Data Output for Channel 2:
Write
Low Byte data
to BASE +8.
Write
High Byte data
to BASE +9.
Write
CMD
00110100
to BASE +10.
Move data to B1 Code
9. To pre-load Data Output for Channel 3:
Write
Low Byte data
to BASE +8.
Write
High Byte data
to BASE +9.
Write
CMD 00110110
to BASE +10.
Move data to B1 Code
10. To simultaneously update all DAC channels:
Write
CMD 0101xxxx
to BASE+10.
Move SPAN/DATA B1>>B2 All
Channels
