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WinSystems PCM-MIO-A-1, Product Manual

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WinSystems PCM-MIO-A-1 Product Manual Download Page 16

PCM-MIO-A-1/Configuration

v1.0

www.winsystems.com

Page 16

7.3.4 J5, J6 - PC/104 Connectors

The PC/104 bus is electrically equivalent to the 16-bit ISA bus. Standard 

PC/104 I/O cards can be populated on PCM-MIO-A-1’s connectors, located 

at J5 and J6. The interface does not support hot swap capability. The PC/

104 bus connector pin definitions are provided here for reference. Refer 

to the 

PC/104 Bus Specification

 for specific signal and mechanical 

specifications. 

Layout and Pin Reference

Notes:

# = Active low signal
Rows C and D are not required on 8-bit modules.
B10 and C19 are key locations. WINSYSTEMS uses key pins as connections to GND.
Signal timing and function are as specified in ISA specification.
Signal source/sink current differ from ISA values.

Diagram

Pin

Name

Pin

Name

Diagram

Pin

Name

Pin

Name

J5

D0

GND

C0

GND

J6

A1

IOCHK#

B1

GND

D1

MEMCS16#

C1

SBHE#

A2

SD7

B2

RESET

D2

IOCS16#

C2

LA23

A3

SD6

B3

+5V

D3

IRQ10

C3

LA22

A4

SD5

B4

IRQ

D4

IRQ11

C4

LA21

A5

SD4

B5

-5V

D5

IRQ12

C5

LA20

A6

SD3

B6

DRQ2

D6

IRQ15

C6

LA19

A7

SD2

B7

-12V

D7

IRQ14

C7

LA18

A8

SD1

B8

SRDY#

D8

DACK0#

C8

LA17

A9

SD0

B9

+12V

D9

DRQ0

C9

MEMR#

A10

IOCHRDY

B10

KEY

D10

DACK5#

C10

MEMW#

A11

AEN

B11

SMEMW#

D11

DRQ5

C11

SD8

A12

SA19

B12

SMEMR#

D12

DACK6#

C12

SB9

A13

SA18

B13

IOW#

D13

DRQ6

C13

SB10

A14

SA17

B14

IOR#

D14

DACK7#

C14

SB11

A15

SA16

B15

DACK3#

D15

DRQ7

C15

SB12

A16

SA15

B16

DRQ3

D16

+5V

C16

SB13

A17

SA14

B17

DACK1#

D17

MASTER#

C17

SB14

A18

SA13

B18

DRQ1

D18

GND

C18

SB15

A19

SA12

B19

REFRESH#

D19

GND

C19

KEY

A20

SA11

B20

BCLK

A21

SA10

B21

IRQ7

A22

SA9

B22

IRQ6

A23

SA8

B23

IRQ5

A24

SA7

B24

IRQ4

A25

SA6

B25

IRQ3

A26

SA5

B26

DACK2#

A27

SA4

B27

TC

A28

SA3

B28

BALE

A29

SA2

B29

+5V

A30

SA1

B30

OSC

A31

SA0

B31

GND

A32

GND

B32

GND

Summary of Contents for PCM-MIO-A-1

Page 1: ...Inc 2890 112th Street Grand Prairie Texas 75050 817 274 7553 info winsystems com www winsystems com PCM MIO A 1 16 Channel 16 bit Analog Inputs 8 Channel 12 bit Analog Outputs and 48 Digital I O Prod...

Page 2: ...ess statutory implied or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement WINSYSTEMS Inc makes no warranty of mercha...

Page 3: ...nfiguration 10 7 1 Component Layout 10 7 1 1 Top View 10 7 2 Jumper Reference 11 7 2 1 J7 Base I O Address Jumpers 11 7 2 2 J10 Digital I O VCC Enable Jumpers 12 7 3 Connector Reference 12 7 3 1 J2 AD...

Page 4: ...2 22 8 2 3 Command Register 23 8 2 4 Command Codes 24 8 2 5 Address Codes 24 8 2 6 Span Codes 24 8 2 7 Readback Enable 25 8 2 8 D A Interrupts 25 8 2 9 D A Examples 25 8 3 Registers 27 8 3 1 Register...

Page 5: ...817 274 7553 Monday through Friday between 8 AM and 5 PM Central Standard Time CST Refer to the WINSYSTEMS website at http www winsystems com for other accessories including cable drawings and pinout...

Page 6: ...lity in the system IRQs 0 1 2 8 and 13 are not supported 3 3 Analog to Digital The PCM MIO A 1 analog to digital conversion inputs are implemented by using two 16 bit Linear Technology LTC 1859CG devi...

Page 7: ...e on the PCM MIO A AD 1 Two 4 channel 12 bit digital to analog D A LTC 2704CGW 12 Output ranges 0 5 V 0 10 V 5 V or 10 V 2 5 V 2 5 V to 7 5 V Each channel independently programmable for output type an...

Page 8: ...rters The DACs provide 12 bit outputs via the Linear Technology LTC2704 6 Specifications The PCM MIO A 1 adheres to the following specifications and requirements Feature Specification Electrical VCC 5...

Page 9: ...e between failure MTBF a MTBF hours 1074379 MTBF years 122 646 RoHS Compliant Yes Operating Systems Compatible with Windows and Linux a A MTBF measurement is based on a statistical sample and is not i...

Page 10: ...ault base I O address J3 Analog output J1 Analog output J8 Digital I O J9 Digital I O J10 Digital I O Vcc enabled J5 PC 104 connector J6 PC 104 connector Item Description Reference J1 J3 D A Analog Ou...

Page 11: ...ential port addresses The base address is jumper selectable at J7 Take care to choose an I O area that does not conflict with other resources in the system Address bits A0 to A4 are not selectable J7...

Page 12: ...algorithm and an internal sample and hold circuit to convert an analog input signal to 16 bit digital data The output is two s complement binary for bipolar mode and offset binary for unipolar mode P...

Page 13: ...t Linear Technology LTC 2704 devices These SoftSpan quad digital to analog converters DACs are software programmable for either unipolar or bipolar mode with specific voltage ranges on a per channel b...

Page 14: ...the Lattice MachXO2 FPGA with WINSYSTEMS WS16C48 ASIC compatible programmed logic The 48 lines are each individually programmable as input or output and the first 24 lines are capable of fully latche...

Page 15: ...GND 35 Port 3 Bit 6 34 GND 33 Port 0 Bit 7 34 GND 33 Port 3 Bit 7 32 GND 31 Port 1 Bit 0 32 GND 31 Port 4 Bit 0 30 GND 29 Port 1 Bit 1 30 GND 29 Port 4 Bit 1 28 GND 27 Port 1 Bit 2 28 GND 27 Port 4 B...

Page 16: ...es Diagram Pin Name Pin Name Diagram Pin Name Pin Name J5 D0 GND C0 GND J6 A1 IOCHK B1 GND D1 MEMCS16 C1 SBHE A2 SD7 B2 RESET D2 IOCS16 C2 LA23 A3 SD6 B3 5V D3 IRQ10 C3 LA22 A4 SD5 B4 IRQ D4 IRQ11 C4...

Page 17: ...device operation The specific options of each register are detailed here Notes 1 Accessed when REGISTER SELECT BASE 3 bit 3 00 2 Accessed when REGISTER SELECT BASE 3 bit 3 01 3 Accessed when REGISTER...

Page 18: ...en REGISTER SELECT BASE 7 bit 3 1 3 0 Disabled 1 Enabled Register Address Base Read Write 7 6 5 4 3 2 1 0 DATA_LO 4 R LOW ORDER DATA BYTE DATA BIT 7 DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BI...

Page 19: ...input channels are measured with respect to GND Both the and inputs are sampled simultaneously so common mode noise is rejected Range Selection Bits 3 and 2 of the command register determine the inpu...

Page 20: ...insystems com Page 20 Input Range Selection Examples of Multiplexer Options Examples of multiplexer options and changing the MUX assignment on The fly are shown below 3 2 UNI GAIN INPUT RANGE 0 0 5 V...

Page 21: ...xxx to bits 3 4 of BASE 3 Select access to CMD 2 Write CMD selection to BASE 2 Set MUX channel operation range 3 Read data from BASE 0 and discard Lo_Byte unknown data 4 Read data from BASE 1 and disc...

Page 22: ...dditional register select bit MASTER IRQ DA2 SELECT If this bit is set to 1 reading BASE 15 results in the status of the Master Interrupt Status Register Register Address Base Read Write 7 6 5 4 3 2 1...

Page 23: ...and register used to configure the span and load the data The command word consists of a 4 bit command and a 4 bit address as shown Each DAC contains a command register used to Register Address Base R...

Page 24: ...C n Set by Previous Command B1 Span DAC n 0 0 1 1 Write to B1 Span DAC n Set by Previous Command B1 Span DAC n 0 1 0 0 Update B1 B2 DAC n Set by Previous Command B2 Span DAC n 0 1 0 1 Update B1 B2 All...

Page 25: ...t access to Resource Register 2 Write IRQ selection 0 15 hex to bits 3 0 of BASE 10 xF Hex IRQ 15 3 Write xxxxxx1 BASE 11 to enable the IRQ Enabling an interrupt for D A2 can be achieved in the same m...

Page 26: ...te Span data 0000xxxx to BASE 8 Where xxxx Span 3 Write 00000000 zero BASE 9 High order byte for Span 4 Write CMD 01100xxx to BASE 10 Where xxx DAC channel 5 Write Low Byte data to BASE 8 6 Write High...

Page 27: ...ible programmed logic This provides 48 lines of digital I O There are 17 unique registers within the WS16C48 Write High Byte data to BASE 9 Write CMD 00110000 to BASE 10 Move data to B1 Code 7 To pre...

Page 28: ...reflects the combined state of the INT_ID0 through INT_ID2 registers When any of the lower three bits are set it indicates that an interrupt is pending on the I O port corresponding to the bit positio...

Page 29: ...n interrupt is enabled for the corresponding port and bit When cleared to 0 the bit s edge detection interrupt is disabled Note that this register can be used to individually clear a pending interrupt...

Page 30: ...TRM RELAY Industrial PC 104 relay board 16 SPDT relays Termination board ISM TRM ISO OUT Termination board 24 isolated outputs Termination board ISM TRM ISO IN Termination board 24 isolated inputs Ter...

Page 31: ...ly s minimum load then the power supply does not regulate properly and can cause damage to the PCM MIO A 1 Power Harness Minimize the length of the power harness This reduces the amount of voltage dro...

Page 32: ...breaking any connections I O Connections OFF Turn off all I O connections before connecting them to the PCM MIO A 1 or any other I O cards Connecting hot signals can cause damage whether the embedded...

Page 33: ...hem could cause the embedded computer module to be flexed Avoid cutting the PCM MIO A 1 Never use star washers or any fastening hardware that cut into the PCM MIO A 1 Avoid over tightening of mounting...

Page 34: ...manuals are updated often Periodically check the WINSYSTEMS website http www winsystems com for revisions Check pinouts Always check the pinout and connector locations in the manual before plugging in...

Page 35: ...PCM MIO A 1 Mechanical Drawings v1 0 www winsystems com Page 35 Appendix B Mechanical Drawings The mechanical drawing for the PCM MIO A 1 is shown below...

Page 36: ...Products shall remain vested in WINSYSTEMS until complete payment is made by Customer Title to any Software shall remain vested in WINSYSTEMS or WINSYSTEMS licensor from whom WINSYSTEMS has obtained...

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