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WM_PRJ_Q2686_PTS_001-010
June 30, 2009
Q2686 Wireless CPU
®
3.16
Reset Signal (~RESET)
This signal is used to force a reset procedure by providing low level for at least
200
μ
s. This signal must be considered as an emergency reset only. A reset
procedure is already driven by the internal hardware during the power-up
sequence.
This signal may also be used to provide a reset to an external device (at power-
up only). If no external reset is necessary, this input may be left open. If used
(emergency reset), it must be driven by an open collector or an open drain.
The Wireless CPU
®
remains in reset mode as long as the ~RESET signal is held
low.
CAUTION: This signal should only be used for “emergency” resets.
An Operating System reset is to be preferred to a hardware reset.
Reset sequence:
To activate the "emergency" reset sequence, the ~RESET signal must be set to
low for 200
μ
s minimum. As soon as the reset is completed, the AT interface
answers "OK" to the application.
RESET mode
I
BB+RF
=20 to
40mA
~RESET
STATE OF
THE
Wireless CPU
®
Wireless
CPU
®
READY
Rt = Min
1
:200
μ
s
or Typ
2
= 40ms
AT answers “OK”
Wireless CPU
®
READY
SIM and network
dependent
Wireless CPU
®
ON
I
BB+RF
<120mA
without loc update
Ct = Typ:34ms
Figure 11: Reset sequence waveform
At power-up, the ~RESET time (Rt) is carried out after switching ON the
Wireless CPU
®
. It is generated by the internal Q2686 Wireless CPU
®
voltage
supervisor.
The ~RESET time is provided by the internal RC component. To keep the same
time, it is not recommended to connect another R or C component on the
~RESET signal. Only a switch or an open drain gate is recommended.
Ct is the cancellation time required for the Wireless CPU
®
Q2686 initialization.
Ct is automatically carried out by the Q2686 Wireless CPU
®
after a hardware
reset.
