VMIC VMIVME-7740 Product Manual Download Page 1

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12090 South Memorial Parkway

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VMIVME-7740

Single Board Pentium III Processor-Based VMEbus SBC

Product Manual

500-007740-000 Rev. A

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Summary of Contents for VMIVME-7740

Page 1: ...al Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 VMIVME 7740 Single Board Pentium III Processor Based VMEbus SBC Product Manual 500 007740 000 Rev A S t o c...

Page 2: ...12090 South Memorial Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 S t o c k C h e c k c o m...

Page 3: ...Logic Link SRTbus TESTCAL The Next Generation PLC The PLC Connection TURBOMODULE UCLIO UIOD UPLC Visual Soft Logic Control ler VMEaccess VMEbus Access VMEmanager VMEmonitor VMEnet VMEnet II and VMEpr...

Page 4: ...12090 South Memorial Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 S t o c k C h e c k c o m...

Page 5: ...s 23 VMEbus Features 26 VMIVME 7740 Product Options 27 Chapter 2 Installation and Setup 29 Unpacking Procedures 29 Hardware Setup 30 Installation 35 BIOS Setup 36 Front Panel Connectors 36 PMC Expansi...

Page 6: ...g 57 Reading 59 Mode Definitions 62 Flash Disk 63 Configuration 63 Functionality 64 Advanced Configuration 64 Watchdog Timer 67 Time of Day Registers 69 Time of Day Alarm Registers 70 Watchdog Alarm R...

Page 7: ...QuickBoot 94 Setting The Time 94 Setting The Date 94 Legacy Diskette 95 Floppy Drive A 95 Floppy Drive B 95 Primary Master Slave 95 Secondary Master 96 Keyboard Features 96 NumLock 96 Key Click 96 Key...

Page 8: ...102 Assign Interrupt to USB 102 Legacy USB Support 102 Power 103 Security 104 Boot Menu 105 Exit Menu 106 Exit Saving Changes 106 Exit Discarding Changes 106 Load Setup Defaults 106 Discard Changes 10...

Page 9: ...ice Interrupt Map 120 PCI Device Interrupt Map 122 Appendix F Sample C Software 123 Directory CPU 124 CPU C 124 FILE CPU H 134 FILE FLAT C 135 FILE FLAT H 143 FILE PCI C 145 FILE PCI H 149 FILE UNIVER...

Page 10: ...VMIVME 7740 Product Manual 10 S t o c k C h e c k c o m...

Page 11: ...Clearing the Timer Interrupt Status Register 55 Figure 4 4 82C54 Diagram 56 Figure 4 5 Internal Timer Diagram 57 Figure 4 6 Typical System Configuration 63 Figure 4 7 Watchdog Alarm Block 67 Figure A...

Page 12: ...VMIVME 7740 Product Manual 12 S t o c k C h e c k c o m...

Page 13: ...ster Bit Descriptions 48 Table 3 6 Supported Graphics Video Resolutions 50 Table 4 1 I O Address of the Control Word Register and Timers 55 Table 4 2 Control Word Format 57 Table 4 3 ST Select Timer 5...

Page 14: ...VMIVME 7740 Product Manual 14 122 S t o c k C h e c k c o m...

Page 15: ...The VMEbus functions are available by programming the VMIVME 7740 s PCI to VMEbus bridge according to the references defined in this volume and or in the second volume dedicated to the optional PCI t...

Page 16: ...e provides information relative to the care and maintenance of the unit Appendix A Connector Pinouts illustrates and defines the connectors included in the unit s I O ports Appendix B System Driver So...

Page 17: ...programming the VMIVME 7740 include Pentium III Processors and Related Products Intel Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 800 548 4752 www intel com Intel 440GX PCIset 82443GX PCI...

Page 18: ...VMEbus International Trade Association VITA 7825 East Gelding Dr Suite No 104 Scottsdale AZ 85260 602 951 8866 FAX 602 951 0720 www vita com The following is useful information related to remote Ethe...

Page 19: ...definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do...

Page 20: ...assis of the equipment which normally includes all exposed metal structures Alternating current power line Direct current power line Alternating or direct current power line STOP informs the operator...

Page 21: ...ent from the memory bus Every effort has been made in the manual to clarify this by referring to registers and logical entities in I O space by prefixing I O addresses as such Thus a register at I O 1...

Page 22: ...VMIVME 7740 Product Manual 22 S t o c k C h e c k c o m...

Page 23: ...rator 4 Mbyte SGRAM Video Memory Resolutions up to 1600x1200x56k colors Battery backed clock calendar Front panel reset switch and miniature speaker On board port for a keyboard and mouse Ultra IDE ha...

Page 24: ...with a PS 2 Style Adapter M K Front Panel PS 2 Style Connector Mini DIN Circular female Adapter Y Cable Supplied Super VGA Video Controller with 4 Mbyte SGRAM SVGA Front Panel DB15HD High Density fema...

Page 25: ...IDE Accelerator PIIX4E C T 69030 Universe IIB Intel 82559 82443GX SUPER I O with RTC SMC FDC37C67X CF Socket P7 Flash BIOS 16 bit Timers 32 Kbyte NVRAM Pentium III PS 2 Keyboard Mouse Watchdog Timer...

Page 26: ...ured programmable VMEbus requester ROR RWD and BCAP modes are supported System Controller autodetection Complete VMEbus master access through five separate Protected mode memory windows Figure 1 2 ill...

Page 27: ...of vendor configurations The options and current details available with the VMIVME 7740 are defined in the device specification sheet available from your VMIC representative DTB Master DTB Slave Data...

Page 28: ...28 1 VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 29: ...ght have occurred during shipment All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service together with a request for advice concer...

Page 30: ...lled header jumpers The physical location of the jumpers and connectors for the single board CPU are illustrated in Figure 2 1 on page 31 The definitions of the CPU board jumpers and connectors are in...

Page 31: ...ure 2 1 VMIVME 7740 CPU Board I O Port and Jumper Locations SVGA Port Reset Keyboard Mouse 10BaseT COM 1 PMC COM 2 100 Base Tx 10BaseT 100 Base Tx Sysfail HD 5 V PWR THERM Indicator USB LAN 1 LAN 2 S...

Page 32: ...2 Keyboard Mouse Connector E11 Fan Connector P1 P2 VME Connectors J4 J5 J6 PMC PCI Expansion Connectors J8 USB Connectors E9 E7 E11 E12 Factory Use Only Table 2 2 Timers and NVRAM Battery Select User...

Page 33: ...f power to the unit 2 Install a jumper at E4 3 Power up the unit 4 Turn off the power to the unit and remove the jumper from E4 When power is re applied to the unit the CMOS will be cleared Table 2 5...

Page 34: ...Installed Universe Memory Mapped Installed should not be removed E13 2 4 Installed SYSFAIL Not Asserted Upon Reset Removed SYSFAIL Asserted Upon Reset Installed E14 1 3 Installed Drives VMEbus SYSRES...

Page 35: ...e VMIVME 7740 board For 20 slot VME configurations three 100 CFM fans are recommended 3 Insert the VMIVME 7740 and its attached expansion modules into the chosen VMEbus chassis slot expansion modules...

Page 36: ...the hardware from the moment power is applied The VMIVME 7740 is shipped from the factory with no hard drives configured in CMOS The BIOS Setup program must be run to configure the specific drives at...

Page 37: ...ard drive activity is occurring LED 4 SYSFAIL Red Indicates when a VMEbus SYSFAIL is asserted Figure 2 3 LED Position on the Front Panel RST VMEbus C O M 1 2 L A N 1 S V G A VMIVME 7740 M K M E Z Z A...

Page 38: ...38 2 VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 39: ...r The design includes a high speed microprocessor with current technology memory Reference the VMIC product specifications for available component options Because the design is PC AT compatible it ret...

Page 40: ...tility of I O Works Access with Windows NT 4 0 to configure RAM do not request more than 25 percent of the physical RAM Exceeding the 25 percent limit may result in a known Windows NT bug This may cau...

Page 41: ...FFFFF 128 Kbyte ROM BIOS D8018 DFFFF 32 Kbyte minus 24 bytes NVRAM D8016 D8017 2 bytes Board ID Register BID 0x7740 D8014 D8015 2 bytes VME BERR Address Modifier Register VBAMR D8010 D8013 4 bytes VM...

Page 42: ...rts hard and floppy drive controllers video system real time clock system timers and interrupt controllers are addressed in this region of I O space The BIOS initializes and configures all these regis...

Page 43: ...OM2 Serial I O 16550 Compatible 2FF 36F 113 Reserved 370 377 8 Super I O Chip Secondary Floppy Disk Controller 378 37F 8 Super I O Chip LPT1 Parallel I O 380 3E7 108 Reserved 3E8 3EE 7 UART COM3 Seria...

Page 44: ...IRQ0 to IRQ7 at the PIC The IBM PC AT computer added eight more IRQx lines numbered IRQ8 to IRQ15 by cascading a second slave PIC into the original master PIC IRQ2 at the master PIC was committed as t...

Page 45: ...int Same as Real Mode 04 4 ALU Overflow Same as Real Mode 05 5 Print Screen Array Bounds Check 06 6 Invalid OpCode 07 7 Device Not Available 08 8 IRQ0 Timer Tick Double Exception Detected 09 9 IRQ1 Ke...

Page 46: ...Real Mode 1D 29 Video Parameter Table Pntr Same as Real Mode 1E 30 Floppy Parm Table Pntr Same as Real Mode 1F 31 Video Graphics Table Pntr Same as Real Mode 20 32 DOS Terminate Program Same as Real...

Page 47: ...2 User Available Same as Real Mode 67 70 103 112 Reserved by DOS Same as Real Mode 71 113 IRQ9 Not Assigned 72 114 IRQ10 Not Assigned 73 115 IRQ11 Not Assigned 74 116 IRQ12 Mouse 75 117 IRQ13 Math Cop...

Page 48: ...ave its own up to a maximum of four functions or any combination thereof A single function can not generate an interrupt request on more than one INTx line The slave PCI accepts the VMEbus interrupts...

Page 49: ...RQ4 IRQ5 IRQ7 IRQ8 IRQ9 IRQ10 IRQ12 PCI to VMEbus INTA PCI INTERRUPT IRQ6 IRQ3 IRQ11 IRQ13 IRQ14 IRQ15 CPU INTR CONNECTIONS MAPPED BY BIOS PMC EXPANSION SITE SERR BRIDGE V M E b u s Timer Keybd Com 2...

Page 50: ...s support resolutions and refresh rates beyond 640 x 480 at 60 Hz Do not attempt to drive a monitor to a resolution or refresh rate beyond its capability Floppy disks supplied with the VMIVME 7740 als...

Page 51: ...cal solution to networking by allowing the use of existing telephone wiring and connectors The RJ 45 connector is used with the 10BaseT standard 10BaseT has a maximum length of 100 m from the wiring h...

Page 52: ...52 3 VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 53: ...s three software controlled general purpose timers along with a programmable Watchdog Timer for synchronizing and controlling multiple events in embedded applications The VMIVME 7740 also provides a b...

Page 54: ...ed in the Timer Interrupt Status section below Timer Interrupt Status A single interrupt IRQ5 is used by all three Timers A Timer Interrupt Status register is provided in order to determine which Time...

Page 55: ...for clearing PC AT IRQ5 Timer Programming Architecture The VMIVME 7740 Timers are mapped in I O address space starting at 500 see Table 4 1 The Timers consisting of three 16 bit timers and a Control...

Page 56: ...ter and the present state of the output and load count flag The Status Word is available via the Read Back command see the Reading section on page 59 The Timer is labeled TE Timer Element It is a 16 b...

Page 57: ...y written to by the user the count is written to the TR registers then latched to the TE Figure 4 5 Internal Timer Diagram Writing The Timers are programmed by first writing a Control Word and then th...

Page 58: ...Write RW1 RW0 Description 0 0 Timer Latch Command see Reading section 0 1 Read Write least significant byte only 1 0 Read Write most significant byte only 1 1 Read Write least significant byte first...

Page 59: ...ecting the timing in process Like a Control Word the Timer Latch Command is written to the Control Word Register I O Address 503 see Table 4 1 The Select Timer bits ST1 ST0 see Table 4 3 select one of...

Page 60: ...l be held until it is read The Read Back command can also be used to latch the timer status by setting the Status bit 0 and selecting the Timers Status of a Timer is accessed by a read from that Timer...

Page 61: ...oth the Count bit D5 and Status bit D4 to zero 0 in the Read Back command If this technique is used the first read operation of the Timer will return the status while the next one or two reads dependi...

Page 62: ...N counter Once a Control Word and an initial count are written to the Timer the initial count is loaded on the next Clock cycle When the count decrements to 1 an interrupt is generated The Timer then...

Page 63: ...a typical system consisting of the VMIVME 7740 with a resident Flash Disk a hard drive attached to the Primary IDE interface and a floppy drive attached to the floppy interface Figure 4 6 Typical Sys...

Page 64: ...l system consists of the VMIVME 7740 with its resident Flash Disk configured as the Secondary IDE device a hard drive attached to the Primary IDE interface and a floppy drive attached to the floppy in...

Page 65: ...has been installed on the Flash Disk that modifies the Master Boot Record MBR then the following steps are required to rewrite the MBR for DOS 11 Run FDISK MBR 12 Run FORMAT C use the s option if you...

Page 66: ...ering each logical device sequentially until they are all named then doing the same sequential lettering of each logical partition on the second hard disk NOTE Drive letter changes caused by adding a...

Page 67: ...register see Table 3 1 is used to enable this option The System Command Register is 2 bytes wide located at memory address D800E NOTE The Watchdog Timer Interrupt output must be set to Level Mode see...

Page 68: ...n binary The Watchdog Alarm Registers are Registers C and D and information stored in these registers is in BCD Table 4 12 Watchdog Registers Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 69: ...For AM Bit 5 is set to zero 0 and for PM Bit 5 is set to one 1 The total range of this register in the 12 hour format is 01 AM to 12 AM and 01 PM to 12 PM When Register 4 is in 24 hour format Bit 6 i...

Page 70: ...Register 2 4 and 6 respectively Bit 7 of registers 3 5 and 7 is a mask bit The mask bits when active logic one 1 disable the use of the particular Time of Day Alarm register in the determination of th...

Page 71: ...rs C and D will disable the Watchdog Alarm feature Command Register Register B is the Command Register Within this register are mask bits control bits and flag bits The following paragraphs describe e...

Page 72: ...t occurs This bit is reset when any of the Watchdog Alarm registers are accessed When the Interrupt Output is set to Pulse Mode see Bit 4 Interrupt Pulse Mode or Level Mode the flag will be set to a l...

Page 73: ...Timer the System Command Register the VME BERR Address Register the VME BERR Address Modifier Register and the Board ID Register and are unavailable for SRAM use See the Watchdog Timer section The NVR...

Page 74: ...74 4 VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 75: ...or adjacent boards were disturbed when inserting or removing the board from the chassis 8 Quality of cables and I O connections If products must be returned obtain a RMA Return Material Authorization...

Page 76: ...76 5 VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 77: ...ble VMEbus Controller has several connectors for its I O ports Figure A 1 shows the locations of the connectors on the VMIVME 7740 Wherever possible the VMIVME 7740 uses connectors and pinouts typical...

Page 78: ...Manual Figure A 1 VMIVME 7740 Connector and Jumper Locations SVGA Port Reset Keyboard Mouse 10BaseT COM 1 PMC COM 2 100 Base Tx 10BaseT 100 Base Tx Sysfail HD 5 V PWR THERM Indicator USB LAN 1 LAN 2 S...

Page 79: ...Figure A 2 Ethernet Connector Pinout ETHERNET CONNECTOR 10BaseT 100BaseTx PIN Signal Name 1 TD Transmit Data 2 TD Transmit Data 3 RD Receive Data 4 TX_CT_OUT Transmit Center Tap Out 5 TX_CT_OUT Trans...

Page 80: ...strates the pinout Figure A 3 Video Connector Pinout 5 15 6 1 VIDEO CONNECTOR PIN DIRECTION FUNCTION 1 Out Red 2 Out Green 3 Out Blue 4 Reserved 5 Ground 6 Ground 7 Ground 8 Ground 9 Reserved 10 Groun...

Page 81: ...e refer to the product specification sheet for ordering information Figure A 4 Serial Connector Pinouts 5 9 6 1 COM 1 and COM 2 SERIAL PORT CONNECTORS D9 PIN DIR RS 232 SIGNAL FUNCTION 1 In DCD Data C...

Page 82: ...B port uses an industry standard four position shielded connector Figure A 5 shows the pinout of the USB connector Figure A 5 USB Connector and Pinout Pin Signal Function 1 USBV USB Power 2 USB USB Da...

Page 83: ...ard Connector Pinout Table A 1 Keyboard Mouse Y Splitter Cable Keyboard Mouse Pin Dir Function Pin Dir Function 1 In Out Keyboard Data 1 In Out Mouse Data 2 Unused 2 Unused 3 Ground 3 Ground 4 5V 4 5V...

Page 84: ...quest 1 13 VME_LWORD Long Word 14 VME_WRITE Write Enable 14 VME_BR2 Bus Request 2 14 VME_AM5 Address Modifier 5 15 GND Ground 15 VME_BR3 Bus Request 3 15 VME_A 23 VME Address Line 23 16 VME_DTACK Data...

Page 85: ...graphic Address 2 13 N C No Connect 14 N C No Connect 14 N C No Connect 15 GA 3 Geographic Address 3 15 N C No Connect 16 N C No Connect 16 N C No Connect 17 GA 4 Geographic Address 4 17 N C No Connec...

Page 86: ...round 14 VME_D 16 VME Data Line 16 14 IDESELA IDE Control 15 GND Ground 15 VME_D 17 VME Data Line 17 15 N C No Connect 16 GND Ground 16 VME_D 18 VME Data Line 18 16 N C No Connect 17 A1 IDE Control 17...

Page 87: ...NN 19 P8 19 13 CONN 20 P8 20 14 CONN 21 P8 21 14 GND Ground 15 CONN 22 P8 22 15 CONN 23 P8 23 16 CONN 24 P8 24 16 GND Ground 17 CONN 25 P8 25 17 CONN 26 P8 26 18 CONN 27 P8 27 18 GND Ground 19 CONN 28...

Page 88: ...88 A VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 89: ...e performance of each of these PCI based subsystems the VMIVME 7740 is provided with software drivers compatible with DOS Windows 98 SE and Windows NT operating systems The following paragraphs provid...

Page 90: ...ntel 82559 and install the appropriate 8255X driver Manual Installation of the 8255X Driver If Windows 98 SE has already been installed on your hard drive it may be necessary to manually install the 8...

Page 91: ...Select the NetBEUI Protocol only click Next 11 Click Next to install selected components 12 Click Next to start the network connection 13 Step through the remaining screens providing the data pertinen...

Page 92: ...n the Change Display window Click OK 26 Proceed as directed removing the driver disk from the floppy drive Restart the computer to activate the new settings When the system reboots the Invalid Display...

Page 93: ...drive configuration or system memory The parameters shown throughout this section are the default values Help Window The help window on the right side of each menu displays the help text for the curr...

Page 94: ...through the available choices or type in the information Setting The Date Press the left or right arrow key to move the cursor to the desired field month day year Press the PGUP or PGDN key to step t...

Page 95: ...a second floppy drive The default is Disabled Primary Master Slave The VMIVME 7740 has the capability of utilizing one IDE hard disk drive on the Primary Master bus The default setting is Auto The Pr...

Page 96: ...or disables the Keyboard Auto Repeat Rate and Delay settings When disabled the values in the Typematic Rate and Delay are ignored The default is Disabled Keyboard Auto Repeat Rate Chars Sec If the Key...

Page 97: ...al amount of memory installed in the system in Kbytes Extended Memory The Extended Memory field is for informational purposes only and cannot be modified by the user This field displays the total amou...

Page 98: ...of console to be used The options are PC ANSI or VT100 The default is PC ANSI Flow Control Enables or disables Flow Control The options are No Flow Control XON XOFF or CTS RTS The default is CTS RTS C...

Page 99: ...ache memory where it is stored until processed by the CPU The default is Enabled 3KRHQL 6HWXS 8WLOLW 0 1 GYDQFHG 3RZHU 6HFXULW RRW LW WHP 6SHFLILF HOS QVWDOOHG 2 6 2WKHU QDEOH 3 1R 6HOHFW WKH RSHUDWLQ...

Page 100: ...DVH N N ULWH DFN DFKH WHQGHG 0HPRU UHD ULWH DFN DFKH LVDEOHG DFKH LVDEOHG LVDEOHG LVDEOHG LVDEOHG LVDEOHG LVDEOHG LVDEOHG LVDEOHG HOS 6HOHFW WHP KDQJH 9DOXHV 6HWXS HIDXOWV 6 LW 6HOHFW 0HQX QWHU 6HOHFW...

Page 101: ...h Advanced Chipset Control Selecting Advanced Chipset Control opens the menu below Use this menu to change the values in the chipset register for optimizing your system s performance Graphics Aperture...

Page 102: ...sabled Checking Only EC Checking and Correction ECC or Checking Correction with Scrubbing ECC Scrub The default is Disabled SERR Signal Configuration Select ECC error conditions that SERR will be asse...

Page 103: ...SRZHU 0D LPXP 3HUIRUPDQFH FRQVHUYHV SRZHU EXW DOORZV JUHDWHVW V VWHP SHUIRUPDQFH 7R DOWHU WKHVH VHWWLQJV FKRRVH XVWRPL HG 7R WXUQ RII SRZHU PDQDJHPHQW FKRRVH LVDEOHG 38 7KURWWOLQJ RZQ 7KUHVKROG LVDEOH...

Page 104: ...LOLW 6HFXULW WHP 6SHFLILF HOS 6HFXULW 6XSHUYLVRU 3DVVZRUG FRQWUROV FFHVV WR WKH VHWXS XWLOLW 6HW 6XSHUYLVRU 3DVVZRUG QWHU 6HW 6XSHUYLVRU 3DVVZRUG QWHU 1HZ 3DVVZRUG RQILUP 1HZ 3DVVZRUG HOS 6HOHFW WHP K...

Page 105: ...pses devices with a or next to them 3KRHQL 6HWXS 8WLOLW 0 1 GYDQFHG 3RZHU 6HFXULW RRW LW WHP 6SHFLILF HOS 5HPRYDEOH HYLFHV DUG ULYH H V XVHG WR YLHZ RU FRQILJXUH GHYLFHV QWHU H SDQGV RU FROODSVHV GHYL...

Page 106: ...ny changes to CMOS Load Setup Defaults Load System defaults as defined at the factory Discard Changes Discard any changes without exiting the Setup program Save Changes Save any changes made without e...

Page 107: ...Features Setup 110 Introduction The VMIVME 7740 includes a LANWorks option which allows the VMIVME 7740 to be booted from a network This appendix describes the procedures to enable this option and the...

Page 108: ...he arrow keys highlight Managed PC Boot Agent MBA and press the ENTER key to continue with the system boot Boot Menu The second method of enabling the LANWorks BIOS option is to press the F2 key durin...

Page 109: ...RU FROODSVHV GHYLFHV ZLWK D RU WUO QWHU H SDQGV DOO 6KLIW HQDEOHV RU GLVDEOHV D GHYLFH DQG PRYHV WKH GHYLFH XS RU GRZQ Q PD PRYH UHPRYDEOH GHYLFH EHWZHHQ DUG LVN RU 5HPRYDEOH LVN G UHPRYH D GHYLFH WK...

Page 110: ...RG 53 RQILJ 0HVVDJH QDEOHG 0HVVDJH 7LPHRXW 6HFRQGV RRW IDLOXUH 3URPSW DLW IRU NH RRW DLOXUH 1H W 6 GHYLFH 8VH FXUVRU NH V WR HGLW 8S RZQ FKDQJH ILHOG HIW 5LJKW FKDQJH YDOXH 6 WR TXLW UHVWRUH SUHYLRXV...

Page 111: ...W IDLOXUH 3URPSW DLW IRU NH RRW DLOXUH 1H W 6 GHYLFH 8VH FXUVRU NH V WR HGLW 8S RZQ FKDQJH ILHOG HIW 5LJKW FKDQJH YDOXH 6 WR TXLW UHVWRUH SUHYLRXV VHWWLQJV WR VDYH 0DQDJHG 3 RRW JHQW 0 Y 26 QWHJUDWHG...

Page 112: ...112 D VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 113: ...ME 7740 is unique in that the BIOS cannot be removed it must be used in the initial boot cycle A custom application like a revised operating system for example can only begin to operate after the BIOS...

Page 114: ...must be familiar in order to override the initial BIOS configuration the device addresses and the device interrupts This appendix reviews the details of these addresses and interrupts and provides a...

Page 115: ...elerator PIIX4E C T 69030 Universe IIB Intel 82559 82443GX SUPER I O with RTC SMC FDC37C67X CF Socket P7 Flash BIOS 16 bit Timers 32 Kbyte NVRAM Pentium III PS 2 Keyboard Mouse Watchdog Timer NVRAM Co...

Page 116: ...4E 2200 Mission College Blvd P O Box 58119 Santa Clara CA 95052 8119 4 Intel 82559 10 100 Mb s Ethernet LAN Controller Intel www intel com 5 Intel 69030 Technical Reference Manual Intel Corporation 22...

Page 117: ...8 USA ISBN 0 929392 15 9 10 82C54 CHMOS Programmable Internal Timer Intel Corporation 2200 Mission College Blvd P O Box 58119 Santa Clara CA 95052 8119 11 DS 1384 Watchdog Timekeeping Controller Dalla...

Page 118: ...the ISA devices with the exception of the real time clock keyboard and programmable timer are relocatable to almost anywhere within the standard 1 Kbyte of I O address space Table E 1 defines the spe...

Page 119: ...address space and then assigns where in that space the device will reside This functionality enables PCI devices to be located in either Memory or I O address space Board ID Register Nonrelocatable 0x...

Page 120: ...illustrated in Figure E 2 on page 121 within the PCI to ISA Bridge PIIX4E 82371EB section of the diagram To maintain backward compatibility with PC XT systems IBM chose to use the new IRQ9 input on th...

Page 121: ...GE V M E b u s Timer Keybd Com 2 Com 1 Timer Floppy Control Interrupt 8 15 Lpt 1 Real Tm Clock Mouse Math PCI PCI Co Proc PIRQ0 PIRQ1 PIRQ2 PIRQ3 IRQ2 INTB INTC INTD INTA INTA SVGA INTA Connection is...

Page 122: ...ra Universe II Universe CA91C142 0x10E3 0x0 AD19 INTA PIRQ0 6 N A PCI Expansion Site N A Board Specific Board Specific N A INTA PIRQ3 N A N A N A Board Specific Board Specific N A INTB PIRQ0 N A N A N...

Page 123: ...iles are provided to the VMIVME 7740 user on disk 320 500052 006 Sample Application C Code for the VMIVME 7740 included in the distribution disk set Because of the wide variety of environments in whic...

Page 124: ...h include stdio h include string h include conio h include ctype h include dos h include flat h include pci h include universe h include cpu h define PCI_BASE16 0x10000000 PCI BASE for A16 define VME...

Page 125: ..._status void far interrupt old_vect void unsigned char int_line char user 80 FPTR un_regs void main void unsigned char pci_devices int test_int to_cnt unsigned long temp_dword unsigned char bus dev_fu...

Page 126: ...cate PCI device Tundra Universe n exit 1 test_int read_configuration_area READ_CONFIG_BYTE bus dev_func 0x3C temp_dword if test_int SUCCESSFUL int_line temp_dword 0xFF else printf Unable to read confi...

Page 127: ..._US VRAI_CTL_VAS_16 enable VME with master slave set for big endian and time out 64 us fw_word CPUREGS VME_EN MEC_BE SEC_BE BYPASS_EN BTO_64 BTO_EN place additional code here do_exit 0 end main void d...

Page 128: ...nit_int purpose Using the interrupt assigned the original vector is saved and the vector to the new ISR is installed The programmable interrupt controller PIC is enabled parameters none return value n...

Page 129: ...QB irq_rcvd enable interrupt 11 outp 0xa1 pic2_org 0xF7 break case 0xc old_vect getvect IRQC save vector for IRQ 12 setvect IRQC irq_rcvd enable interrupt 12 outp 0xa1 pic2_org 0xEF break case 0xd old...

Page 130: ...MAP1_A 0 map all ERR STAT ints to lint 0 INTA fw_long un_regs LINT_MAP2_A 0 map all MB LM ints to lint 0 INTA enable mailbox 0 ints only fw_long un_regs LINT_EN_A LINT_EN_MBOX0 int_status 0 enable ini...

Page 131: ...e 0xa setvect IRQA old_vect break case 0xb setvect IRQB old_vect break case 0xc setvect IRQC old_vect break case 0xd setvect IRQD old_vect break case 0xe setvect IRQE old_vect break case 0xf setvect I...

Page 132: ...nable tmp_status disable asm 386P push eax push ebx int_status fr_long un_regs LINT_STAT_A read interrupt status fw_long un_regs LINT_STAT_A int_status clear status check for mailbox interrupt if int_...

Page 133: ...es fw_long un_regs MBOX0_A 0 fw_long un_regs MBOX1_A 0 fw_long un_regs MBOX2_A 0 fw_long un_regs MBOX3_A 0 tmp_status fr_long un_regs LINT_STAT_A read interrupt status fw_long un_regs LINT_STAT_A tmp_...

Page 134: ...0002 slave endian conversion big endian define SEC_LE 0x0000 slave endian conversion little endian define BERR_LATCH_EN 0x0004 buss error latch enable define BTO_EN 0x0008 bus timeout timer enable def...

Page 135: ...s define RAMPORT 0x70 define KB_PORT 0x64 define PCNMIPORT 0xA0 define INBA20 0x60 define INBA20ON 0xDF define INBA20OFF 0xDD macro to clear keyboard port define kx while inp KB_PORT 2 define local Gl...

Page 136: ...ar address to a far pointer void far linear_to_seg FPTR lin void far p FP_SEG p unsigned int lin 4 FP_OFF p unsigned int lin 0xF return p Adjust the GS register s limit to 4GB Note interrupts are enab...

Page 137: ...p RAMPORT inp RAMPORT 0x80 call protected mode code protinit gdtptr Turn interrupts back on enable Turn NMI back on outp RAMPORT inp RAMPORT 0x7F void protinit struct fword address asm 386P push ds ld...

Page 138: ...t asm 386P mov bx 8 mov gs bx mov es bx and al 0xfe mov cr0 eax int fr_byte FPTR adr int d asm 386P xor ax ax zero gs mov gs ax mov eax adr mov al byte ptr gs eax mov d ax return d int fr_word FPTR ad...

Page 139: ...d long fr_long FPTR adr long d asm 386P xor ax ax zero gs mov gs ax mov eax adr mov eax dword ptr gs eax mov d eax return d void fw_byte FPTR a int d asm 386P xor ax ax zero gs mov gs ax mov eax a mov...

Page 140: ...d asm 386P xor ax ax zero gs mov gs ax mov eax a mov ebx d mov dword ptr gs eax ebx flat move long void fml_string FPTR d FPTR s long n asm 386P have to use ES for string move push es save es xor ax...

Page 141: ...mov gs ax mov es ax mov edi d This is the destination pointer mov esi s This is the source pointer mov ecx n This is the number of words rep movs word ptr es edi word ptr gs esi pop es give back es fl...

Page 142: ...142 F VMIVME 7740 Product Manual mov ecx n This is the number of bytes rep movs byte ptr es edi byte ptr gs esi pop es give back es S t o c k C h e c k c o m...

Page 143: ...d int limit unsigned int base unsigned int access unsigned int hi_limit static struct _GDT GDT 2 0 0 0 0 Null selector slot 0xFFFF 0 0x9200 0x8F 4 Gig data segment FWORD pointer to GDT struct fword un...

Page 144: ...FPTR flat read byte void fw_byte FPTR int flat write byte int fr_word FPTR flat read word void fw_word FPTR int flat write word long fr_long FPTR flat read long void fw_long FPTR long flat write long...

Page 145: ...signed char bus_number unsigned char device_and_function int ret_status unsigned short ax bx flags _CX device_id _DX vendor_id _SI index _AH PCI_FUNCTION_ID _AL FIND_PCI_DEVICE geninterrupt 0x1a ax _A...

Page 146: ...device_and_function unsigned char register_number unsigned long data int ret_status unsigned short ax flags unsigned long ecx _BH bus_number _BL device_and_function _DI register_number _AH PCI_FUNCTI...

Page 147: ...e_and_function unsigned char register_number unsigned long value int ret_status unsigned short ax flags _BH bus_number _BL device_and_function _ECX value _DI register_number _AH PCI_FUNCTION_ID _AL fu...

Page 148: ...740 Product Manual void outpd unsigned short port unsigned long value _DX port _EAX value __emit__ 0x66 0xEF unsigned long inpd unsigned short port _DX port __emit__ 0x66 0xED return _EAX S t o c k C...

Page 149: ...x0C define WRITE_CONFIG_DWORD 0x0D PCI Return codes define SUCCESSFUL 0x00 define NOT_SUCCESSFUL 0x01 Prototypes int find_pci_device unsigned short device_id unsigned short vendor_id unsigned short in...

Page 150: ...150 F VMIVME 7740 Product Manual unsigned char register_number unsigned long value void outpd unsigned short port unsigned long value unsigned long inpd unsigned short port S t o c k C h e c k c o m...

Page 151: ...served unsigned long pci_u1 unimplemented unsigned long pci_r1 0x02 reserved unsigned long pci_misc1 PCI config miscellaneous 1 reg unsigned long pci_u2 0x30 unimplemented unsigned long lsi0_ctl PCI s...

Page 152: ...special cycle compare data reg unsigned long scyc_swp PCI special cycle swap data reg unsigned long lmisc PCI miscellaneous reg unsigned long slsi PCI special PCI slave image unsigned long l_cmderr P...

Page 153: ...nsigned long dcpp DMA command packet pointer unsigned long urB reserved unsigned long dgcs DMA general control and status reg unsigned long d_llue DMA linked list update enable reg unsigned long urC 0...

Page 154: ...AM codes reg unsigned long urE 0x2bc reserved unsigned long vsi0_ctl VMEbus slave image 0 control reg unsigned long vsi0_bs VMEbus slave image 0 base address reg unsigned long vsi0_bd VMEbus slave ima...

Page 155: ...error log unsigned long vsi4_ctl VMEbus slave image 4 control reg unsigned long vsi4_bs VMEbus slave image 4 base address reg unsigned long vsi4_bd VMEbus slave image 4 bound address reg unsigned lon...

Page 156: ...image 0 control reg define LSI0_BS_A 0x104 PCI slave image 0 base address reg define LSI0_BD_A 0x108 PCI slave image 0 bound address reg define LSI0_TO_A 0x10C PCI slave image 0 translation offset re...

Page 157: ...fine LSI5_BD_A 0x1BC PCI slave image 5 bound address reg define LSI5_TO_A 0x1C0 PCI slave image 5 translation offset reg define LSI6_CTL_A 0x1C8 PCI slave image 6 control reg define LSI6_BS_A 0x1CC PC...

Page 158: ...TATID_A 0x338 VME interrupt status ID in IRQ6 define V7_STATID_A 0x33C VME interrupt status ID in IRQ7 define LINT_MAP2_A 0x340 PCI interrupt map2 define VINT_MAP2_A 0x344 VME interrupt map2 define MB...

Page 159: ...VRAI_BS_A 0xF74 VMEbus register access image base address define VCSR_CTL_A 0xF80 VMEbus CSR control reg define VCSR_TO_A 0xF84 VMEbus CSR translation reg define V_AMERR_A 0xF88 VMEbus AM code error...

Page 160: ...r dmas using linked lists typedef struct dma_command_pkt unsigned long dma_dctl DMA transfer control reg unsigned long dma_dtbc DMA transfer byte count reg unsigned long dma_dla DMA PCI bus address re...

Page 161: ...S 0x00000001 R W target I O enable pci_class PCI configuration class register define PCI_CLASS_BASE 0x06000000 R base class code define PCI_CLASS_SUB 0x00800000 R sub class code define PCI_CLASS_PROG...

Page 162: ...fine LSI_CTL_VAS_32 0x00020000 R W VMEbus address space A32 define LSI_CTL_VAS_R1 0x00030000 R W VMEbus address space RSVD1 define LSI_CTL_VAS_R2 0x00040000 R W VMEbus address space RSVD2 define LSI_C...

Page 163: ...addr MASK define LSI5_BD 0xFFFF0000 R W PCI slave image 5 bound addr MASK define LSI6_BD 0xFFFF0000 R W PCI slave image 6 bound addr MASK define LSI7_BD 0xFFFF0000 R W PCI slave image 7 bound addr MA...

Page 164: ...timer 256 us define LMISC_CRT_3 0x30000000 R W coupled request timer 512 us define LMISC_CRT_4 0x40000000 R W coupled request timer 1024 us define LMISC_CRT_5 0x50000000 R W coupled request timer 2048...

Page 165: ...I VME define DCTL_VDW_08 0x00000000 R W VMEbus max data width D08 define DCTL_VDW_16 0x00400000 R W VMEbus max data width D16 define DCTL_VDW_32 0x00800000 R W VMEbus max data width D32 define DCTL_VD...

Page 166: ...VON1 0x00000000 R W VME aligned DMA xfer cnt DONE define DGCS_VON2 0x00100000 R W VME aligned DMA xfer cnt 256 define DGCS_VON3 0x00200000 R W VME aligned DMA xfer cnt 512 define DGCS_VON4 0x00300000...

Page 167: ...e DGCS_INT_VERR 0x00000002 R W interrupt on VERR define DGCS_INT_M_ERR 0x00000001 R W interrupt on protocol error d_llue DMA linked list update enable register define D_LLUE_UPDATE 0x80000000 R W PCI...

Page 168: ...0x00200000 R W Location monitor 1 received define LINT_STAT_LM0 0x00100000 R W Location monitor 0 received define LINT_STAT_MBOX3 0x00080000 R W MAILBOX 3 received define LINT_STAT_MBOX2 0x00040000 R...

Page 169: ...0000000 R W PCI int LINT 4 for VME IRQ7 define LINT_MAP0_VIRQ7_5 0x50000000 R W PCI int LINT 5 for VME IRQ7 define LINT_MAP0_VIRQ7_6 0x60000000 R W PCI int LINT 6 for VME IRQ7 define LINT_MAP0_VIRQ7_7...

Page 170: ...5 define LINT_MAP0_VIRQ4_0 0x00000000 R W PCI int LINT 0 for VME IRQ4 define LINT_MAP0_VIRQ4_1 0x00010000 R W PCI int LINT 1 for VME IRQ4 define LINT_MAP0_VIRQ4_2 0x00020000 R W PCI int LINT 2 for VME...

Page 171: ...e LINT_MAP0_VIRQ2_3 0x00000300 R W PCI int LINT 3 for VME IRQ2 define LINT_MAP0_VIRQ2_4 0x00000400 R W PCI int LINT 4 for VME IRQ2 define LINT_MAP0_VIRQ2_5 0x00000500 R W PCI int LINT 5 for VME IRQ2 d...

Page 172: ...T 5 for VME OWN define LINT_MAP0_VOWN_6 0x00000006 R W PCI int LINT 6 for VME OWN define LINT_MAP0_VOWN_7 0x00000007 R W PCI int LINT 7 for VME OWN lint_map1 PCI interrupt map 1 register define LINT_M...

Page 173: ...L define LINT_MAP1_SW_INT_0 0x00000000 R W PCI int LINT 0 for SW_INT define LINT_MAP1_SW_INT_1 0x00100000 R W PCI int LINT 1 for SW_INT define LINT_MAP1_SW_INT_2 0x00200000 R W PCI int LINT 2 for SW_I...

Page 174: ...700 R W PCI int LINT 7 for VERR define LINT_MAP1_LERR_0 0x00000000 R W PCI int LINT 0 for LERR define LINT_MAP1_LERR_1 0x00000010 R W PCI int LINT 1 for LERR define LINT_MAP1_LERR_2 0x00000020 R W PCI...

Page 175: ...able VMEbus int SW_IACK define VINT_EN_VERR 0x00000400 R W enable PCIbus int VERR define VINT_EN_LERR 0x00000200 R W enable PCIbus int LERR define VINT_EN_DMA 0x00000100 R W enable PCIbus int DMA defi...

Page 176: ...0020 R WC VMEbus int LINT5 define VINT_STAT_LINT4 0x00000010 R WC VMEbus int LINT4 define VINT_STAT_LINT3 0x00000008 R WC VMEbus int LINT3 define VINT_STAT_LINT2 0x00000004 R WC VMEbus int LINT2 defin...

Page 177: ...x00700000 R W VME int 7 for LINT5 define VINT_MAP0_LINT4_D 0x00000000 R W VME int disable for LINT4 define VINT_MAP0_LINT4_1 0x00010000 R W VME int 1 for LINT4 define VINT_MAP0_LINT4_2 0x00020000 R W...

Page 178: ...MAP0_LINT1_4 0x00000040 R W VME int 4 for LINT1 define VINT_MAP0_LINT1_5 0x00000050 R W VME int 5 for LINT1 define VINT_MAP0_LINT1_6 0x00000060 R W VME int 6 for LINT1 define VINT_MAP0_LINT1_7 0x00000...

Page 179: ...0600 R W VME int 6 for VERR define VINT_MAP1_VERR_7 0x00000700 R W VME int 7 for VERR define VINT_MAP1_LERR_D 0x00000000 R W VME int disable for LERR define VINT_MAP1_LERR_1 0x00000010 R W VME int 1 f...

Page 180: ...define VX_STATID_ID 0x000000FF R VME status ID MASK lint_map2 local interrupt Map 2 register define LINT_MAP2_LM3_0 0x00000000 R W PCI int LINT 0 for LOC MON3 define LINT_MAP2_LM3_1 0x10000000 R W PCI...

Page 181: ...fine LINT_MAP2_LM1_3 0x00300000 R W PCI int LINT 3 for LOC MON1 define LINT_MAP2_LM1_4 0x00400000 R W PCI int LINT 4 for LOC MON1 define LINT_MAP2_LM1_5 0x00500000 R W PCI int LINT 5 for LOC MON1 defi...

Page 182: ...BOX3 define LINT_MAP2_MB3_6 0x00006000 R W PCI int LINT 6 for MAILBOX3 define LINT_MAP2_MB3_7 0x00007000 R W PCI int LINT 7 for MAILBOX3 define LINT_MAP2_MB2_0 0x00000000 R W PCI int LINT 0 for MAILBO...

Page 183: ...or MAILBOX0 define LINT_MAP2_MB0_1 0x00000001 R W PCI int LINT 1 for MAILBOX0 define LINT_MAP2_MB0_2 0x00000002 R W PCI int LINT 2 for MAILBOX0 define LINT_MAP2_MB0_3 0x00000003 R W PCI int LINT 3 for...

Page 184: ...BOX2 define VINT_MAP2_MB2_5 0x00000500 R W VME int VIRQ 5 for MAILBOX2 define VINT_MAP2_MB2_6 0x00000600 R W VME int VIRQ 6 for MAILBOX2 define VINT_MAP2_MB2_7 0x00000700 R W VME int VIRQ 7 for MAILBO...

Page 185: ...080 R W semaphore 0 sema1 semaphore 1 register define SEMA1_SEM7 0x80000000 R W semaphore 7 define SEMA1_SEM6 0x00800000 R W semaphore 6 define SEMA1_SEM5 0x00008000 R W semaphore 5 define SEMA1_SEM4...

Page 186: ...burst size 32 define MAST_CTL_PABS_64 0x00001000 R W PCI aligned burst size 64 define MAST_CTL_PABS_128 0x00002000 R W PCI aligned burst size 128 define MAST_CTL_BUS_NO 0x000000FF R W PCI bus number M...

Page 187: ...bus size 64 bits define MISC_STAT_DY4AUTO 0x08000000 R DY4 auto ID enable define MISC_STAT_MYBBSY 0x00200000 R universe NOT busy define MISC_STAT_DY4DONE 0x00080000 R DY4 auto ID done define MISC_STAT...

Page 188: ...VMEbus slave image 0 base address register define VSI0_BS 0xFFFFF000 R W VME slave image 0 base add MASK define VSI1_BS 0xFFFF0000 R W VME slave image 1 base add MASK define VSI2_BS 0xFFFF0000 R W VM...

Page 189: ...AI_CTL_AM_DP 0x00C00000 R W AM code both define VRAI_CTL_AM_U 0x00100000 R W AM code non priv define VRAI_CTL_AM_S 0x00200000 R W AM code supervisory define VRAI_CTL_AM_US 0x00300000 R W AM code both...

Page 190: ...sr_clr VMEbus CSR bit clear register define VCSR_CLR_RESET 0x80000000 R W board reset define VCSR_CLR_SYSFAIL 0x40000000 R W VMEbus sysfail define VCSR_CLR_FAIL 0x20000000 R board fail vcsr_set VMEbus...

Page 191: ...and data address include stdlib h include stdio h include dos h unsigned char far b_ptr unsigned int far w_ptr unsigned long far l_ptr unsigned int far buf_ptr static unsigned long pat 4 0x55555555 0...

Page 192: ...pat x for i 0x18 i 0x8000 i b_ptr bdat bdat bdat b_ptr unsigned char far buf_ptr bdat unsigned char pat x for i 0x18 i 0x8000 i brd b_ptr if bdat brd printf FAILED nBYTE DATA ADDR Fp WR 2X RD 2X n b_p...

Page 193: ...TA LONGS 4 patterns for x 0 x 4 x l_ptr unsigned long far MK_FP 0xD800 0x18 ldat unsigned long pat x for i 0x18 i 0x8000 i 4 l_ptr ldat ldat ldat l_ptr unsigned long far MK_FP 0xD800 0x18 ldat unsigne...

Page 194: ...far MK_FP 0xD800 0x18 for i 0x18 i 0x8000 i 4 l_ptr i l_ptr unsigned long far MK_FP 0xD800 0x18 for i 0x18 i 0x8000 i 4 lrd l_ptr if lrd i printf FAILED nDATA ADDR ADDR Fp WR 8X RD 8X n l_ptr i lrd e...

Page 195: ...GPI_T2 0x40 PIX General Purpose Input 14 tmr 2 define GPI_T3 0x20 PIX General Purpose Input 13 tmr 3 define GPO_T1 0x40 PIX General Purpose Output 30 tmr 1 define GPO_T2 0x10 PIX General Purpose Outpu...

Page 196: ...CW_M0 0x00 W Mode 0 define CW_M1 0x02 W Mode 1 define CW_M2 0x04 W Mode 2 define CW_M3 0x06 W Mode 3 define CW_M4 0x08 W Mode 4 define CW_M5 0x0A W Mode 5 define CW_BCD 0x01 W Binary Coded Decimal def...

Page 197: ...ter int unsigned int void read_counter int unsigned int unsigned char global variables unsigned char bus dev_func the following globals are used in other files as extern variables unsigned char tmr_st...

Page 198: ..._int SUCCESSFUL printf nUnable to locate power management device on PCI bus n do_exit 1 get base address from config area test_int read_configuration_area READ_CONFIG_DWORD bus dev_func 0x40 temp_dwor...

Page 199: ..._timer_int verify all three counters can generate an interrupt counters 1 2 3 printf nTesting all three 16 bit counters for interrupt setup for interrupts to occur t1_count 0 t2_count 0 t3_count 0 t1...

Page 200: ...trol word outp timer_base TIMER_CNTL CW_SC1 CW_LSBMSB CW_M2 tmr_status 0 test_int 100 load_counter 3 0xFFFF do if t3_count t3 break test_int delay 1 while test_int disable timers by reloading the cont...

Page 201: ...f t2 printf TIMER 2 failed n if t3 printf TIMER 3 failed n do_exit 2 do orderly exit do_exit 3 end main void do_exit int xit_code if xit_code 1 restore_orig_int outp gpo_base gpo_org if xit_code 3 xit...

Page 202: ...unsigned long t3_count timer 3 count extern unsigned char tmr_status extern unsigned int gpi_base extern unsigned int gpo_base extern unsigned int timer_base extern unsigned char pic1_org extern unsig...

Page 203: ...et all three GPO outputs to 1 to allow int status registers to function outp gpo_base gpo_org GPO_T1 GPO_T2 GPO_T3 enable init_timer_int restore_orig_int purpose Using the interrupt assigned the origi...

Page 204: ...value none void load_counter int counter unsigned int count int lsb msb lsb count 0xff msb count 8 switch counter case 1 select counter 1 LSB then MSB mode 2 outp timer_base TIMER_CNTL CW_SC0 CW_LSBM...

Page 205: ...er read_counter purpose Reads the appropriate counter in the appropriate bank with the remaining count and status parameters int counter 1 2 3 for COUNTER 1 2 or 3 unsigned int count remaining count u...

Page 206: ...se TIMER_CNTR2 0xFF lsb inp timer_base TIMER_CNTR2 0xFF msb inp timer_base TIMER_CNTR2 0xFF msb msb 8 count lsb msb break case 3 select counter 3 LSB then MSB outp timer_base TIMER_CNTL CW_RBC CW_RB_C...

Page 207: ...1 t1_count outp gpo_base gpo_org GPO_T1 clear timer 1 status bit if tmr_status GPI_T2 t2_count outp gpo_base gpo_org GPO_T2 clear timer 2 status bit if tmr_status GPI_T3 t3_count outp gpo_base gpo_org...

Page 208: ...208 F VMIVME 7740 Product Manual pop ebx pop eax enable S t o c k C h e c k c o m...

Page 209: ...define CLK_DAYAL 0x07 01 07 M 0 0 0 0 define CLK_DATE 0x08 01 31 0 0 define CLK_MONTH 0x09 01 12 0 define CLK_YRS 0x0A 00 99 define WD_CMD 0x0B command register define WD_MSEC 0x0C milli second watch...

Page 210: ...RESET Jumper wd_ptr unsigned char far MK_FP 0xD800 0 set WatchDog Alarm Mask 1 deactivated and update with 0 time wd_ptr WD_CMD WD_TE WD_WAM wd_ptr WD_MSEC 0 load with 0 to disable wd_ptr WD_SEC 0 lo...

Page 211: ...211 Directory WATCHDOG F time t printf START DATE TIME 24s n n ctime t do time t printf CURRENT DATE TIME 24s r ctime t delay 250 while kbhit end main S t o c k C h e c k c o m...

Page 212: ...212 F VMIVME 7740 Product Manual S t o c k C h e c k c o m...

Page 213: ...ntroller 122 Digital Semiconductor s 21143 controller 51 interrupt logic 49 F Floppy Disk Drive 95 Floppy Drive A 95 Floppy Drive B 95 floppy mapping 118 functional diagram 27 G graphics video resolut...

Page 214: ...X4 122 Power on Self Test 114 programmable time 42 protected mode 41 45 R Read Back Command 59 real mode 41 45 real time clock 42 references 17 refresh rates 50 Return Material Authorization RMA numbe...

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