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Summary of Contents for VMIVME-7697

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 VMIVME 7697 Pentium III Processor Based VMEbus CPU Product Manual 500 007697 000 Rev B 7 Feb 2000 Artisan Technology Group Quality Instrumen...

Page 3: ...2090 South Memorial Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 4: ...net Soft Logic Link SRTbus TESTCAL The Next Generation PLC The PLC Connection TURBOMODULE UCLIO UIOD UPLC Visual Soft Logic Control ler VMEaccess VMEmanager VMEmonitor VMEnet VMEnet II and VMEprobe ar...

Page 5: ...2090 South Memorial Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 6: ...29 Chapter 3 Installation and Setup 31 Unpacking Procedures 31 Hardware Setup 32 Installation 40 BIOS Setup 41 Front Panel Connectors 41 PMC Expansion Site Connectors 41 LED Definition 42 Chapter 4 P...

Page 7: ...te TWSS Register Offset 30h 70 Timer Enable Interrupt TEI Register Offset 34h 72 Timer Interrupt Status TIS Register Offset 38h 73 Watchdog Timer 74 Time of Day Registers 76 Time of Day Alarm Register...

Page 8: ...psets 106 Bus Master IDE Driver for Windows 95 106 Windows NT Version 4 0 108 Appendix C Award BIOS 111 System BIOS Setup Utility 112 Standard CMOS Setup 113 Setting The Date 113 Setting The Time 113...

Page 9: ...SDRAM CAS Lat RAS to CAS 120 SDRAM RAS Precharge Time 120 SDRAM CAS Latency Time 121 SDRAM Precharge Control 121 DRAM Data Integrity Mode 121 System BIOS Cacheable 121 Video RAM Cacheable 121 8 Bit I...

Page 10: ...d Mem Base Addr 127 Integrated Peripherals 128 IDE HDD Block Mode 128 IDE Primary Secondary Master PIO 128 IDE Primary Secondary Slave PIO 128 IDE Primary Secondary Master UDMA 129 IDE Primary Seconda...

Page 11: ...itiate Wide Negotiation 141 Send Start Unit Command 141 Advanced Configuration Options 142 Host Adapter BIOS 142 Support Removable Disks Under BIOS as Fixed Disks 142 Extended BIOS Translation for DOS...

Page 12: ...C Software 159 Directory SRAM 160 FILE SRAM C 160 Directory Timers 162 FILE TIMER C 162 FILE TIMERS C 166 TIMERS H 181 Directory VME 184 FILE CPU C 184 FILE CPU H 197 FILE UNIVERSE H 198 Directory WAT...

Page 13: ...VMIVME 7697 Product Manual 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 14: ...Block 74 Figure 4 3 Typical System Configuration 81 Figure A 1 VMIVME 7697 Connector Locations 88 Figure A 2 Ethernet Connector Pinout 89 Figure A 3 Video Connector Pinout 90 Figure A 4 Parallel Port...

Page 15: ...VMIVME 7697 Product Manual 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 16: ...ion Jumper E4 39 Table 3 1 VMIVME 7697 Universe II Based Interface Memory Address Map 45 Table 3 2 VMIVME 7697 I O Address Map 46 Table 3 3 PC AT Hardware Interrupt Line Assignments 48 Table 3 4 PC AT...

Page 17: ...Alarm Registers 78 Table A 1 VMEbus Connector Pinout bottom board 95 Table A 2 VMEbus Connector Pinout top board 97 Table F 1 ISA Device Mapping Configuration 152 Table F 2 PCI Device Mapping Configu...

Page 18: ...oard The VMEbus functions are available by programming the VMIVME 7697 s PCI to VMEbus bridge according to the references defined in this volume and or in the second volume dedicated to the optional P...

Page 19: ...rates and defines the connectors included in the unit s I O ports Appendix B System Drive Software includes detailed instructions for the installation of the drivers during installation of Windows for...

Page 20: ...the VMIVME 7697 include Intel Pentium III Processor at 450 MHz and 500MHz Intel Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 800 548 4752 www intel com Intel 440BX AGP set 82443BX Host Brid...

Page 21: ...c com For a detailed description and specification of the VMEbus please refer to VMEbus Specification Rev C and The VMEbus Handbook VMEbus International Trade Association VITA 7825 East Gelding Drive...

Page 22: ...m Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power c...

Page 23: ...l structures Alternating current power line Direct current power line Alternating or direct current power line The STOP symbol informs the operator the that a practice or procedure should not be perfo...

Page 24: ...ort has been made in the manual to clarify this by referring to registers and logical entities in I O space by prefixing I O addresses as such Thus a register at I O 140 is not the same as a register...

Page 25: ...VMIVME 7697 Product Manual 24 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 26: ...SGRAM Video Memory Resolutions up to 1 600x1200x64K colors Battery backed clock calendar Front panel reset switch and miniature speaker On board ports for a keyboard and mouse Ultra IDE hard drive flo...

Page 27: ...ni DIN Circular female AT Style Mouse Controller with a PS 2 Style Adapter Mouse Front Panel PS 2 Style Connector Mini DIN Circular female AGP Video Controller with 4 Mbyte DRAM SVGA Front Panel DB15H...

Page 28: ...X 32 bit 128 Kbyte PS 2 Watchdog Timer NVRAM Controller DS1384 South Bridge 4MB Video P2 COM Port 2 PMC Site Intel Pentium III Micro Processor North Bridge 82443 BX System Controller AGP Video Control...

Page 29: ...uester ROR RWD and BCAP modes are supported System Controller autodetection Complete VMEbus master access through five separate Protected Mode memory windows Figure 1 2 illustrates the VMIVME 7697 fun...

Page 30: ...tions and current details available with the VMIVME 7697 are defined in the device specification sheet available from your VMIC representative DTB Master DTB Slave Data Transfer Bus DTB Arbitration Pr...

Page 31: ...30 1 VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 32: ...ment All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service together with a request for advice concerning the disposition of the d...

Page 33: ...the user There are five exceptions Password Clear E3 Watchdog Timer E18 VMEbus System Reset Driver E6 VMEbus System Reset Receiver E7 and the VMEbus SYSFAIL On Reset E8 Modifying any other jumper will...

Page 34: ...J1 E17 J2 J5 E1 P3 E14 E2 E16 E15 E18 E9 TP1 Parallel Port SVGA Port Reset Ethernet Status Sysfail HD 5 V PWR Indicator Indicator Keyboard 10BaseT COM 1 COM 2 100 Base Tx Not Shown Not Shown Mouse US...

Page 35: ...eyboard Connector J7 PS 2 Mouse Connector P1 VME Connector P2 VME Connector P3 SO DIMM Connector P4 Parallel Port Connector P5 USB Connector E2 Serial Port Header E14 Serial Port Header E17 EPLD Progr...

Page 36: ...3 Power up the unit until the first screen is displayed 4 Turn off the power to the unit and remove the jumper from E3 When power is reapplied to the unit the CMOS will be cleared Table 2 3 Clear CMOS...

Page 37: ...In Disabled Out Table 2 8 Universe II MEM IO Map Jumper E9 Select Jumper Position Active In Disabled Out Table 2 9 CPU Clock Speed Selection Jumper E13 Select Jumper Position 500MHz 500 MHz CPU 100 MH...

Page 38: ...Jumper E16 Jumper Position CMOS Battery Disabled Out CMOS Battery Enabled In Table 2 12 Watchdog Reset Jumper E18 Select Jumper Position Active In Disabled Out Artisan Technology Group Quality Instrum...

Page 39: ...7 Product Manual Figure 2 2 VMIVME 7697 Top Board Jumper and Connector Locations E4 E3 E5 E1 U1 U2 U5 U7 U3 U8 P2 P1 J2 J1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www...

Page 40: ...oard Connector P4 Compact Flash Connector Table 2 14 SCSI Speed Selection Jumper E1 Select Jumper Position Ultra SCSI In Fast SCSI Out Table 2 15 EPLD In circuit Programming Header E3 Select Jumper Po...

Page 41: ...lot VME configurations three 100 CFM fans are recommended 3 Insert the VMIVME 7697 and its attached expansion modules into the chosen VMEbus chassis slot expansion modules should fill the slots immedi...

Page 42: ...is applied The VMIVME 7697 is shipped from the factory with no hard drives configured in CMOS The BIOS Setup program must be run to configure the specific drives attached Details of the VMIVME 7697 B...

Page 43: ...ates when the Ethernet is linked in 10BaseT mode Green indicates when the Ethernet is linked in 100BaseTx mode Figure 2 4 LED Connector Positions on the Front Panel S RST A L K Y B P A R A L L E L C O...

Page 44: ...he design includes a high speed microprocessor with current technology memory Reference the VMIC product specifications for available component options Because the design is PC AT compatible it retain...

Page 45: ...en the local processor and the VMEbus to prevent a VMEbus master from overwriting the local processor s operating system When using the Configure utility of I O Works Access with Windows NT 4 0 to con...

Page 46: ...0 FFFFF 128 Kbyte ROM BIOS D8018 DFFFF 32 Kbyte Reserved D8016 D8017 2 bytes Board ID Register 0x7697 D8014 D8015 2 bytes VMEBERR Address Modifier Register D8010 D8013 2 bytes MEBERR Address Register...

Page 47: ...ers video system real time clock system timers and interrupt controllers are addressed in this region of I O space The BIOS initializes and configures all these registers properly adjusting these I O...

Page 48: ...COM2 Serial I O 16550 Compatible 2FF 36F 113 Reserved 370 377 8 Super I O Chip Secondary Floppy Disk Controller 378 37F 8 Super I O Chip LPT1 Parallel I O 380 3E7 108 Reserved 3E8 3EE 7 UART COM3 Seri...

Page 49: ...e IBM PC AT computer added eight more IRQx lines numbered IRQ8 to IRQ15 by cascading a second slave PIC into the original master PIC IRQ2 at the master PIC was committed as the cascade input from the...

Page 50: ...LU Overflow Same as Real Mode 05 5 Print Screen Array Bounds Check 06 6 Invalid OpCode 07 7 Device Not Available 08 8 IRQ0 Timer Tick Double Exception Detected 09 9 IRQ1 Keyboard Input Coprocessor Seg...

Page 51: ...Table Pntr Same as Real Mode 1E 30 Floppy Parm Table Pntr Same as Real Mode 1F 31 Video Graphics Table Pntr Same as Real Mode 20 32 DOS Terminate Program Same as Real Mode 21 33 DOS Function Entry Poi...

Page 52: ...e 67 70 103 112 Reserved by DOS Same as Real Mode 71 113 IRQ9 Not Assigned 72 114 IRQ10 Not Assigned 73 115 IRQ11 Not Assigned 74 116 IRQ12 Mouse 75 117 IRQ13 Math Coprocessor 76 118 IRQ14 AT Hard Dri...

Page 53: ...t an interrupt If a device implements a single INTx line it is called INTA if it implements two lines they are called INTA and INTB and so forth For a multifunction device all functions may use the sa...

Page 54: ...ts Table 3 5 NMI Register Bit Descriptions Status Control Register I O Address 061 Read Write Read Only Bit 7 SERR NMI Source Status Read Only This bit is set to 1 if a system board agent detects a sy...

Page 55: ...loppy Control Interrupt 8 15 Lpt 1 Real Tm Clock Mouse Math AT Flash Hard Drv NA NA Coproc PIRQ0 PIRQ1 PIRQ2 PIRQ3 IRQ2 INTB INTC INTD Ethernet INTA SVGA INTA Connection is not complete NMI MAPPER 825...

Page 56: ...to a resolution or refresh rate beyond its capability The VMIVME 7697 s processor includes a 64 bit access to video memory with no wait states Video I O registers are accessed using AGP bus The flopp...

Page 57: ...ted pair cables providing an economical solution to networking by allowing the use of existing telephone wiring and connectors The RJ 45 connector is used with the 10BaseT standard 10BaseT has a theor...

Page 58: ...nd Fast SCSI Internally the SCSI bus is actively terminated therefore there are no peripherals located on the internal SCSI bus The SCSI bus does provide external expansion to accommodate single ended...

Page 59: ...58 3 VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 60: ...nd controlling multiple events in embedded applications The VMIVME 7697 also provides a bootable flash disk system and 128 K byte of nonvolatile battery backed SRAM These features make the unit ideal...

Page 61: ...h timer is set up to be either 32 or 16 bits wide depending on the required time duration Furthermore as illustrated in the block diagram each timer consists of three different 16 bit counters Scale C...

Page 62: ...all the registers which control the timer process There are three Timer Control Registers within the Timer Control Section The Timer Width System State Register determines whether the timers are 32 or...

Page 63: ...or 32 bit operation After the mode and values are initialized the timer is enabled Circuitry Interrupt Status Timer Control Registers Timer 0 Timer Mode Register Timer Setup Signals Local CPU Bus Time...

Page 64: ...ued Each timer is designed to provide an interrupt at repetitive time intervals based on the value placed in the timer Each timer has a resolution of 1 0 s A value of x placed in the timer generates a...

Page 65: ...ies for a 16 bit timer with an initial count of 0x0005 will be as follows 0002 0001 131 075 32 bit 0002 FFFF 196 609 32 bit 0002 0000 196 610 32 bit FFFF 0001 4 294 901 763 32 bit FFFF FFFF 4 294 967...

Page 66: ...o cause an interrupt as a result of timer expiration Specific Upper and Lower Counters can be read to determine elapsed time since the previous read However the Timer Interrupt Status register will mo...

Page 67: ...enabled the timers can be read to determine their present count This is done by first issuing a Read Back command to the particular timer s TMR Register The format of the Read Back command is determin...

Page 68: ...0C D4 Write Read Back command to Timer 0 s TMR Register 2 04 LSB Read the LSB of Lower Counter 3 04 MSB Read the MSB of Lower Counter Table 4 6 32 bit Read Mode Command Example Step Address offset HEX...

Page 69: ...ust be set up and enabled before it can be used Each timer is completely independent of the others Used timers do not need to be set up The VMIVME 7697 includes three timers Each timer is implemented...

Page 70: ...tion 00 Timer 0 Scale Counter SC0 04 Timer 0 Lower Counter LC0 08 Timer 0 Upper Counter UC0 0C Timer 0 Timer Mode Register TMR0 10 Timer 1 Scale Counter SC1 14 Timer 1 Lower Counter LC1 18 Timer 1 Upp...

Page 71: ...hip specifically the Lower Counter The 32 bit width mode is implemented using two 16 bit counters of an 82C54 chip The most significant portion of the 32 bit timer is referred to as the Upper Counter...

Page 72: ...nt portion of the 32 bit Counter Value Also when a timer is 32 bits wide the Scale Counter SCx must be loaded with zeros Although each of the three Counters within an 82C54 Timer are 16 bits wide they...

Page 73: ...ress Offset HEX Data HEX Description 1 0C 7A Timer Mode Register TMR0 byte setting up the Lower Counter of Timer 0 2 04 AD LSB byte of the counter value written to LC0 3 04 45 MSB byte of the counter...

Page 74: ...ress information The register is cleared immediately upon being read Bits 2 to 0 are the status bits for each timer respectively Bit 0 is the status bit for Timer 0 bit 1 is the status bit for Timer 1...

Page 75: ...is 2 bytes wide located at memory address D800E Bit 0 of the Watchdog RESET SYSFAIL SERR Routing Register is used to enable the NMI option Table 4 14 on page 75 The Watchdog Timer Interrupt output mus...

Page 76: ...ase 5 M 12 24 AM PM 10 Hr Hour Alarm BCD 6 Base 6 0 0 0 0 Days BCD 01 07 7 Base 7 M 0 0 0 Day Alarm BCD 01 07 8 Base 8 0 0 10 Date BCD Date BCD 01 31 9 Base 9 Eosc 1 0 10 Mo Months BCD 01 12 A Base A...

Page 77: ...regardless of what value is written to it Register 4 contains the Hours value of the Time of Day The Hours can be represented in either 12 or 24 hour format depending on the state of Bit 6 When Bit 6...

Page 78: ...xternal Time of Day registers are halted This is the recommended method The second technique for reading the Time of Day from the Watchdog Timer is to read the external Time of Day registers without h...

Page 79: ...initialized back to the entered value the Watchdog flag bit is cleared and the Watchdog interrupt output is cleared every time either of the registers are accessed Periodic accesses to the Watchdog Ti...

Page 80: ...zero 0 Time of Day Alarm Interrupt Output will be enabled When set to a logic one 1 Time of Day Alarm Interrupt Output will be disabled Waf Bit 1 Watchdog Alarm Flag This is a read only bit set to a...

Page 81: ...y space Table 4 1 shows the PCI Base Address register NVRAM 1Ch for the battery backed SRAM The battery backed SRAM can be accessed by the CPU at anytime and can be used to store system data that must...

Page 82: ...consisting of the VMIVME 7697 with a resident flash disk a hard drive attached to the Primary IDE interface and a floppy drive attached to the floppy interface Figure 4 3 Typical System Configuration...

Page 83: ...ither a primary partition or an extended partition An extended partition may be subdivided farther into logical partitions Each device may have up to four main partitions one of which may be an extend...

Page 84: ...current partitions any data currently stored in the partitions will be lost 7 Exit FDISK this will cause a reboot then run FDISK again 8 Create a primary partition 9 Create a extended partition and se...

Page 85: ...tinue to assign drive letters to the primary partitions in an alternating fashion between the two drives Next logical partitions will be assigned drive letters starting on the first hard drive letteri...

Page 86: ...turbed when inserting or removing the board from the chassis 8 Quality of cables and I O connections If products must be returned contact VMIC for a Return Material Authorization RMA Number This RMA N...

Page 87: ...86 5 VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 88: ...bus Controller has several connectors for its I O ports Figure A 1 shows the locations of the connectors on the VMIVME 7697 Wherever possible the VMIVME 7697 uses connectors and pinouts typical for an...

Page 89: ...E13 J1 E17 J2 J5 E1 P3 E14 E2 E16 E15 E18 E9 TP1 Parallel Port SVGA Port Reset Ethernet Status Sysfail HD 5 V PWR Indicator Indicator Keyboard 10BaseT COM 1 COM 2 100 Base Tx Not Shown Not Shown Mous...

Page 90: ...Ethernet Connector Pinout ETHERNET CONNECTOR 10BaseT 100BaseTx PIN Signal Name 1 TD Transmit Data 2 TD Transmit Data 3 RD Receive Data 4 NC No Connection 5 NC No Connection 6 RD Receive Data 7 NC No C...

Page 91: ...o Connector Pinout 5 15 6 1 VIDEO CONNECTOR PIN DIRECTION FUNCTION 1 Out Red 2 Out Green 3 Out Blue 4 Reserved 5 Ground 6 Ground 7 Ground 8 Ground 9 Reserved 10 Ground 11 Reserved 12 Reserved 13 Out H...

Page 92: ...l Data D2 5 In Out Bidirectional Data D3 6 In Out Bidirectional Data D4 7 In Out Bidirectional Data D5 8 In Out Bidirectional Data D6 9 In Out Bidirectional Data D7 10 In Acknowledge 11 In Device Busy...

Page 93: ...tion sheet for ordering information Figure A 5 Serial Connector Pinouts 5 9 6 1 COM 1 and COM 2 SERIAL PORT CONNECTORS D9 PIN DIR RS 232 SIGNAL FUNCTION 1 In DCD Data Carrier Detect 2 In RX Receive Da...

Page 94: ...ini DIN PS 2 connector as shown in Figure A 6 Figure A 6 Keyboard Connector Pinout 1 2 3 4 5 6 KEYBOARD CONNECTOR PIN DIR FUNCTION 1 In Out Data 2 Reserved 3 Ground 4 5 V 5 Out Clock 6 Reserved Shield...

Page 95: ...mini DIN PS 2 connector as shown in Figure A 7 Figure A 7 Mouse Connector Pinout 1 2 3 4 5 6 MOUSE CONNECTOR PIN DIR FUNCTION 1 In Out Data 2 Reserved 3 Ground 4 5 V 5 Out Clock 6 Reserved Shield Chas...

Page 96: ...GNAL P2 ROW C SIGNAL 1 D00 BBSY D08 GND 5 V IDE RST 2 D01 BCLR D09 DDP8 GND DDP7 3 D02 ACFAIL D10 DDP9 Reserved DDP6 4 D03 BG0IN D11 DDP10 A24 DDP5 5 D04 BG0OUT D12 DDP11 A25 DDP4 6 D05 BG1IN D13 DDP1...

Page 97: ...D D26 STEP 26 A05 IRQ5 A12 GND D27 WD4TA 27 A04 IRQ4 A11 GND D28 TRK 28 A03 IRQ3 A10 GND D29 RDATA 29 A02 IRQ2 A09 DSKCHG D30 SIDE1 30 A01 IRQ1 A08 GND D31 DIR 31 12 V 5 V STDBY 12 V VCC GND WGATE 32...

Page 98: ...OW A SIGNAL P2 ROW B SIGNAL P2 ROW C SIGNAL 1 NA NA NA SSCD 12 5 V GND 2 NA NA NA GND GND SSCD 13 3 NA NA NA SSCD 14 NA GND 4 NA BG0IN NA GND NA SSCD 15 5 NA BG0OUT NA SSCD PH NA GND 6 NA BG1IN NA SSC...

Page 99: ...D NA SSCD 9 27 NA NA NA SSCD 8 NA GND 28 NA NA NA GND NA SSCD 11 29 NA NA NA SSCD 10 NA NA 30 NA NA NA NA NA Reserved 31 12 V NA 12 V 5 GND NA 32 5 V NA 5 V 5 5 V Reserved Table A 2 VMEbus Connector P...

Page 100: ...r Figure A 10 shows the pinout of the USB connector Figure A 10 USB Connector Pinout USB CONNECTOR PIN SIGNAL FUNCTION 1 USBV USB Power 2 USB USB Data 3 USB USB Data 4 USBG USB Ground Conductors End V...

Page 101: ...100 A VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 102: ...stems the VMIVME 7697 is provided with software drivers compatible with DOS Windows for Workgroups Version 3 11 Windows 95 and Windows NT operating systems The following paragraphs provide instruction...

Page 103: ...NTINUE 8 Under ADD NETWORK ADAPTER click on UNLISTED or UPDATED NETWORK ADAPTER Then click OK 9 Insert the VMIVME 7697 distribution disk marked 320 500043 005 into drive A and type A 32bit WFW311 Then...

Page 104: ...etup the proper connection type for your system Proceed with the following steps to set your network connection type If you are not running a network please skip steps 26 through 30 26 From the PROGRA...

Page 105: ...click on PCI ETHERNET CONTROLLER 11 Select the DRIVER tab and then select CHANGE DRIVER 12 In the SELECT HARDWARE TYPE screen choose NETWORK ADAPTERS and click on OK 13 Insert the Diskette marked 320...

Page 106: ...eled 320 500043 003 into drive A Type A as the files source if not already displayed and click on OK 33 Under SELECT DEVICE choose S3 Trio 3d then click OK 34 When the CHOOSE DISPLAY TYPE screen retur...

Page 107: ...se any running applications 3 The driver files are stored in an integrated application setup program This program is a Windows 95 program that allows the driver files to be INSTALLED or DE INSTALLED I...

Page 108: ...5 directory SYSTEM IOSUBSYS IDEATAPI MPD Windows 95 directory SYSTEM IOSUBSYS PIIXVSD VXD Windows 95 directory INF IDEATAPI INF This driver is not to be used with Windows 98 The setup program must be...

Page 109: ...lick OK 9 Select the above entry on the displayed list click on NEXT 10 Select the NetBEUI Protocol only click on NEXT 11 Click on NEXT to install selected components 12 Click CONTINUE to allow an Aut...

Page 110: ...pe A 32bit and click OK 25 S3 Trio 3d will be displayed in the CHANGE DISPLAY window Click on OK 26 Proceed as directed removing the driver disk from the floppy drive and restart the computer to activ...

Page 111: ...110 B VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 112: ...PnP PCI Configuration 126 Integrated Peripherals 128 Introduction The VMIVME 7697 utilizes the BIOS Basic Input Output system in the same manner as other PC AT compatible computers This appendix desc...

Page 113: ...stem memory The parameters shown throughout this section are the default values 520 3 6 26 026 6 783 87 7 5 62 7 5 1 67 1 5 026 6 783 17 5 5 7 3 5 3 5 6 26 785 6 6 783 683 59 625 3 66 25 36 7 785 6 6...

Page 114: ...ary time clock For example 1 PM is 13 00 00 Press the left or right arrow key to move the cursor to the desired field hour minute seconds Press the PgUp or PgDn key to step through the available choic...

Page 115: ...e default is None Video The VMIVME 7697 has an EGA VGA graphics chip onboard The BIOS supports a secondary video subsystem but it is not selected in Setup The default is EGA VGA Use the PgUp or PgDn k...

Page 116: ...s for informational purposes only and can not be modified by the user This field displays the total RAM installed in the system and the amounts allocated to base extended and other high memory Artisan...

Page 117: ...n the CPU requests data the system transfers the requested data from the main DRAM into the cache memory were it is stored until processed by the CPU The default is Enabled 520 3 6 26 26 785 6 6 783 5...

Page 118: ...n checks normally performed during the POST are omitted decreasing the time required to run the POST The default is Enabled Boot From LAN First When enabled this option allows the CPU to boot off of a...

Page 119: ...determines the rate a character is repeated when a key is held down The options are 6 8 10 12 15 20 24 or 30 characters per second Typematic Delay Msec If the Typematic rate Setting is enabled this de...

Page 120: ...chnology system SMART is a hard drive self diagnostic feature available on some IDE hard drives The default is Disabled Report No FDD For WIN95 Select Yes to release IRQ6 when the system contains no f...

Page 121: ...o accumulate its charge before DRAM refresh If insufficient time is allowed refresh may be incomplete and the DRAM may fail to retain data This field applies only if synchronous DRAM is installed in t...

Page 122: ...formance However if any program writes to this memory area a system error may result The default is Disabled Video RAM Cacheable Selecting Enabled allows caching of the video BIOS ROM at C0000h to C7F...

Page 123: ...GP Aperture Size MB Select the size of the Accelerated Graphics Port AGP aperture The aperture is a portion of the PCI memory address range dedicated for graphics memory address space Host cycles that...

Page 124: ...Savings Minimum power savings Inactivity period is 1 hour in each mode except the hard drive Disabled Turns off all power management features The default is Disabled 520 3 6 26 32 5 0 1 0 17 6 783 5 6...

Page 125: ...to blank The default is Standby Modem Use IRQ Name the interrupt request IRQ line assigned to the modem if any on your system Activity of the selected IRQ awakens the system The default setting is N A...

Page 126: ...is Disabled Wake Up On LAN When Enabled a request from the LAN awakens the system from a soft off state The default is Enabled CPU Clock Throttle When Enabled this allows the power management routines...

Page 127: ...been installed and the system reconfiguration has caused such a serious conflict that the operating system cannot boot The default is Disabled 520 3 6 26 313 3 21 85 7 21 5 62 7 5 1 313 26 QVWDOOHG 1...

Page 128: ...ssigned to When resources are controlled manually assign each system DMA channel as one of the following types depending on the type of device using the interrupt Legacy ISA Devices compliant with the...

Page 129: ...s IDE PIO Programmed Input Output field allows setting a PIO mode 0 4 for the IDE devices that the onboard IDE interface supports Modes 0 through 4 provide successively increased performance In Auto m...

Page 130: ...abled On Chip Secondary PCI IDE The integrated peripheral controller contains an IDE interface with support for two IDE channels Select Enabled to activate each channel separately When this option is...

Page 131: ...MIVME 7697 The options are Standard RS 232C serial port IrDA 1 0 N A MIR 0 57M N A MIR 1 15M N A FIR N A ASK IR N A The default for this setting is Standard Onboard Parallel Port Select an address and...

Page 132: ...E 7697 includes the LANWorks option which allows the VMIVME 7697 to be booted from a network This appendix describes the LANWorks BIOS Setup screen and the procedures to enable this option D Artisan T...

Page 133: ...the Return key This will display the BIOS Features Setup screen 520 3 6 26 026 6 783 87 7 5 62 7 5 1 67 1 5 026 6 783 17 5 5 7 3 5 3 5 6 26 785 6 6 783 683 59 625 3 66 25 36 7 785 6 6 783 86 5 3 66 25...

Page 134: ...HG RRW URP 1 LUVW QDEOHG RRW 6HTXHQFH 6 6 6ZDS ORSS ULYH LVDEOHG RRW 8S ORSS 6HHN QDEOHG RRW 8S 1XP RFN 6WDWXV 2Q DWH 2SWLRQ DVW 7 SHPDWLF 5DWH 6HWWLQJ LVDEOHG 7 SHPDWLF 5DWH KDUV 6HF 7 SHPDWLF HOD 0V...

Page 135: ...he Default Boot field Network Default Selects Network Boot as the default boot device Local Selects a Local Drive as the default boot device Local Boot The following options are available in the Local...

Page 136: ...the procedure for using the utility In this appendix the VMIVME 7697 SCSI adapter will be referred to as the host adapter or as the adapter During boot time the Power On Self Test POST software displa...

Page 137: ...igure the host adapter or run the SCSI disk utilities Select the option and press Enter Press F5 to switch between color and monochrome modes Options Configure View Host Adapter Settings SCSI Disk Uti...

Page 138: ...a W at Bus Device 00 0Ah Configuration SCSI Bus Interface Definitions Host Adapter SCSI ID 7 SCSI Parity Checking Enabled Host Adapter SCSI Termination Low ON High ON Additional Options Boot Device Op...

Page 139: ...accuracy of data transfer on the SCSI bus for each adapter If a device on the SCSI bus does not support SCSI parity then disable the parity checking Most SCSI devices support SCSI parity The default...

Page 140: ...e 0 through 7 on 8 bit or 16 bit adapters The Boot LUN Number default is 0 SCSI Device Configuration Each device on the SCSI bus requires configuration parameters that must be defined prior to device...

Page 141: ...then the adapter automatically transfers the data in asynchronous mode SCSI Device Configuration SCSI Device ID 0 1 2 3 4 5 6 7 Initiate Sync Negotiation yes yes yes yes yes yes yes yes Maximum Sync T...

Page 142: ...to No The Enable Disconnection should be set to yes if the adapter connects to two or more SCSI devices This will optimize SCSI bus performance If the adapter connects to only one SCSI device set the...

Page 143: ...to free up about 16 Kbyte of memory This will also reduce boot time by 60 seconds Support Removable Disks Under BIOS as Fixed Disks This option provides control of removable media drives The default i...

Page 144: ...partition a disk larger than 1 Gbyte The cylinder size increases to 8 Mbyte under extended translation therefore the partition size must be a multiple of 8 Mbyte Requesting a size that is not a multip...

Page 145: ...ir SCSI ID Number and insure that no duplicates are present Selection of a device allows the operator to format or verify the disk on the device AIC 7880 Ultra Ultra W at Bus Device 00 0Ah Select SCSI...

Page 146: ...elect Format disk At the confirmation prompt select Yes to format or No to cancel You cannot abort formatting once it has started Verifying a Disk Using the Verify Disk option the operator can scan a...

Page 147: ...146 E VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 148: ...IOS can not be removed it must be used in the initial boot cycle A custom application like a revised operating system for example can only begin to operate after the BIOS has finished initializing the...

Page 149: ...ride the initial BIOS configuration These include the device addresses and the device interrupts This appendix reviews the details of these addresses and interrupts and provides a reference list for t...

Page 150: ...FDC37C67X 32 bit 128 Kbyte PS 2 Watchdog Timer NVRAM Controller DS1384 South Bridge 4MB Video P2 COM Port 2 PMC Site Intel Pentium III Micro Processor North Bridge 82440 BX System Controller AGP Vide...

Page 151: ...national 503 234 6762 FAX 5 SMC FDC37C67X Enhanced Super I O Controller SMC Component Products Division 300 Kennedy Drive Hauppauge NY 11788 516 435 6000 516 231 6004 FAX 6 ISA EISA Theory and Operati...

Page 152: ...Santa Clara CA 95052 8119 408 765 8080 www intel com 11 Adaptec A IC 7880 Ultra FAST SCSI Host Adapter Adaptec Inc 691 South Milpitas Blvd Milpitas CA 95035 12 S3 Trio 3d AGP Video Controller P O Box...

Page 153: ...the real time clock keyboard and programmable timer are relocatable to almost anywhere within the standard 1 Kbyte of I O address space Table F 1 defines the spectrum of addresses available for recon...

Page 154: ...then assigns where in that space the device will reside This functionality enables PCI devices to be located in either Memory or I O address space VMEBERR Address Register Nonrelocatable 0xD8010 N A...

Page 155: ...155 within the PCI to ISA Bridge PIIX4E 82371EB section of the diagram To maintain backward compatibility with PC XT systems IBM chose to use the new IRQ9 input on the slave PIC to operate as the old...

Page 156: ...er Floppy Control Interrupt 8 15 Lpt 1 Real Tm Clock Mouse Math AT Flash Hard Drv NA NA Coproc PIRQ0 PIRQ1 PIRQ2 PIRQ3 IRQ2 INTB INTC INTD Ethernet INTA SVGA INTA Connection is not complete NMI MAPPER...

Page 157: ...Timer PLX 9052 0x114A 7697 AD25 N A N A 9 N A SCSI Adaptec 7880 0x9004 0x8078 AD29 INTA PIRQ3 11 N A AGP Video S3 Trio 3d 0x5333 0x8904 N A N A N A 12 N A PMC Expansion Site N A Board Specific Board...

Page 158: ...F 4 Using the interrupt steering registers of the 82371AB PIIX4 the user can override the BIOS defaults and map any of the PCI interrupts PIRQ0 3 to any of the following PIC IRQx ISA interrupts IRQ15...

Page 159: ...158 F VMIVME 7697 Product Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 160: ...697 user on disk 320 500043 007 Sample Application C Code for the VMIVME 7697 included in the distribution disk set Because of the wide variety of environments in which the VMIVME 7697 operates the sa...

Page 161: ...stdio h include string h include conio h include dos h include flat h include pci h define DID_7697 0x7697 Device ID define VID_7697 0x114A Vendor ID void main void int test_int unsigned long temp_dwo...

Page 162: ...UCCESSFUL printf nUnable to read SRAM BASE ADDRESS 0x1C in config space n exit 1 sram_base temp_dword 0xFFFFFFF0 extend_seg a20 1 Use the flat write and flat read functions to access the SRAM memory f...

Page 163: ...4 of the manual FILE TIMER C FILE TIMER C include stdlib h include stdio h include string h include conio h include ctype h include dos h include flat h include pci h include timers h define DID_7697...

Page 164: ...CESSFUL printf nUnable to locate 7697 n exit 1 get TIMERS base address from config area test_int read_configuration_area READ_CONFIG_DWORD bus dev_func 0x20 temp_dword if test_int SUCCESSFUL printf nU...

Page 165: ...F load_counter 1 1 0xFFFF load_counter 2 1 0xFFFF read timer interrupt status register to clear any left over status i fr_byte timers_base EXT_TMR_TIS enable all three timers and enable interrupts fw_...

Page 166: ...nter 2 0 0x0000 load_counter 2 1 0xFFFF load_counter 2 2 0x0001 read timer interrupt status register to clear any left over status i fr_byte timers_base EXT_TMR_TIS enable all three timers and interru...

Page 167: ...Q9 0x71 define IRQA 0x72 define IRQB 0x73 define IRQC 0x74 define IRQD 0x75 define IRQE 0x76 define IRQF 0x77 function prototypes void far interrupt irq_rcvd void void init_timer_int void void restore...

Page 168: ...ed and the vector to the new ISR is installed The programmable interrupt controller PIC is enabled Prerequisite The interrupt line to be used must have already been loaded in the global variable param...

Page 169: ...save vector for IRQ 9 setvect IRQ9 irq_rcvd enable interrupt 9 outp 0xa1 pic2_org 0xFD else if int_line 0xA old_vect getvect IRQA save vector for IRQ 10 setvect IRQA irq_rcvd enable interrupt 10 outp...

Page 170: ...2_org 0xEF else if int_line 0xD old_vect getvect IRQD save vector for IRQ 13 setvect IRQD irq_rcvd enable interrupt 13 outp 0xa1 pic2_org 0xDF else if int_line 0xE old_vect getvect IRQE save vector fo...

Page 171: ...Using the interrupt assigned the original vector is restored and the programmable interrupt controller is disabled Prerequisite The interrupt line to be used must have already been loaded in the globa...

Page 172: ...ine 0x9 setvect IRQ9 old_vect else if int_line 0xA setvect IRQA old_vect else if int_line 0xB setvect IRQB old_vect else if int_line 0xC setvect IRQC old_vect else if int_line 0xD setvect IRQD old_vec...

Page 173: ...e appropriate counter in the appropriate bank with the count passed in parameters int bank 0 1 2 for BANK 0 1 or 2 int counter 0 1 2 for COUNTER 0 1 or 2 unsigned int count count to be loaded return v...

Page 174: ...5 fw_byte timers_base BANK0_CNTL CW_SC1 CW_LSBMSB CW_M5 fw_byte timers_base BANK0_CNTR1 unsigned char lsb fw_byte timers_base BANK0_CNTR1 unsigned char msb break case 2 select counter 2 LSB then MSB m...

Page 175: ...NTL CW_SC2 CW_LSBMSB CW_M5 fw_byte timers_base BANK1_CNTR2 unsigned char lsb fw_byte timers_base BANK1_CNTR2 unsigned char msb break break case 2 select BANK 2 switch counter case 0 select counter 0 L...

Page 176: ...unter purpose Reads the appropriate counter in the appropriate bank with the remaining count and status parameters int bank 0 1 2 for BANK 0 1 or 2 int counter 0 1 2 for COUNTER 0 1 or 2 unsigned int...

Page 177: ...B then MSB fw_byte timers_base BANK0_CNTL CW_RBC CW_RB_CNT CW_RB_STAT CW_RB_C1 status fr_byte timers_base BANK0_CNTR1 0xFF lsb fr_byte timers_base BANK0_CNTR1 0xFF msb fr_byte timers_base BANK0_CNTR1...

Page 178: ...k case 1 select counter 1 LSB then MSB fw_byte timers_base BANK1_CNTL CW_RBC CW_RB_CNT CW_RB_STAT CW_RB_C1 status fr_byte timers_base BANK1_CNTR1 0xFF lsb fr_byte timers_base BANK1_CNTR1 0xFF msb fr_b...

Page 179: ...xFF msb fr_byte timers_base BANK2_CNTR0 0xFF msb msb 8 count lsb msb break case 1 select counter 1 LSB then MSB fw_byte timers_base BANK2_CNTL CW_RBC CW_RB_CNT CW_RB_STAT CW_RB_C1 status fr_byte timer...

Page 180: ...K2_CNTR2 0xFF msb msb 8 count lsb msb break break read_counter irq_rcvd purpose Interrupt service routine used to service any of the counters on the 7697 parameters none return value none void interru...

Page 181: ...s tmr_status fr_byte timers_base EXT_TMR_TIS 0xFF Non specific end of interrupt to PIC outp 0x20 0x20 Master end of irq command asm 386P pop ebx pop eax enable Artisan Technology Group Quality Instrum...

Page 182: ...0 0x20 Timer bank 2 counter 0 define BANK2_CNTR1 0x24 Timer bank 2 counter 1 define BANK2_CNTR2 0x28 Timer bank 2 counter 2 define BANK2_CNTL 0x2C Timer bank 2 control define EXT_TMR_CNTL 0x30 Externa...

Page 183: ...efine TE_B2_EN 0x04 RW enable bank 2 timer define TE_B1_EN 0x02 RW enable bank 1 timer define TE_B0_EN 0x01 RW enable bank 0 timer External Timer interrupt status register define TIS_B2_INT 0x04 RW ba...

Page 184: ..._M3 0x06 W Mode 3 define CW_M4 0x08 W Mode 4 define CW_M5 0x0A W Mode 5 define CW_BCD 0x01 W Binary Coded Decimal define CW_RB_CNT 0x00 W Read back count define CW_RB_STAT 0x00 W Read back status defi...

Page 185: ...to be accessed from VME to allow mailbox access include stdlib h include stdio h include string h include conio h include ctype h include dos h include flat h include pci h include universe h include...

Page 186: ...ig_int void void do_exit int global variables unsigned char pic2_org unsigned long mb0_msg unsigned long mb1_msg unsigned long mb2_msg unsigned long mb3_msg unsigned long int_status void far interrupt...

Page 187: ...ord if test_int SUCCESSFUL un_regs FPTR temp_dword else printf Unable to read configuration area 0x10 n exit 1 else printf Unable to locate PCI device Tundra Universe n exit 1 test_int read_configurat...

Page 188: ..._TO_A 0x00000000 PCI_BASE16 fw_long un_regs LSI0_CTL_A LSI_CTL_EN LSI_CTL_VDW_32 LSI_CTL_VAS_16 enable 4K VME to universe regs sht I O 0xC000 to allow mailbox access fw_long un_regs VRAI_BS_A VME_16_R...

Page 189: ...L_A 0 fw_long un_regs LSI6_CTL_A 0 fw_long un_regs LSI7_CTL_A 0 fw_long un_regs VSI0_CTL_A 0 fw_long un_regs VSI1_CTL_A 0 fw_long un_regs VSI2_CTL_A 0 fw_long un_regs VSI3_CTL_A 0 fw_long un_regs VSI4...

Page 190: ...roller PIC is enabled parameters none return value none void init_int void disable Read 8259 slave Programmable Interrupt controller pic2_org inp 0xa1 0xFF slave mask bits switch int_line case 0x9 old...

Page 191: ...ble interrupt 11 outp 0xa1 pic2_org 0xF7 break case 0xc old_vect getvect IRQC save vector for IRQ 12 setvect IRQC irq_rcvd enable interrupt 12 outp 0xa1 pic2_org 0xEF break case 0xd old_vect getvect I...

Page 192: ...g un_regs LINT_MAP0_A 0 map all VME ints to lint 0 INTA fw_long un_regs LINT_MAP1_A 0 map all ERR STAT ints to lint 0 INTA fw_long un_regs LINT_MAP2_A 0 map all MB LM ints to lint 0 INTA enable mailbo...

Page 193: ...obal variable parameters none return value none void restore_orig_int void disable outp 0xa1 pic2_org switch int_line case 0x9 setvect IRQ9 old_vect break case 0xa setvect IRQA old_vect break case 0xb...

Page 194: ...se 0xf setvect IRQF old_vect break end switch fw_long un_regs LINT_EN_A 0 disable all interrupts enable restore_orig_int irq_rcvd purpose Interrupt service routine INTA handler parameters none return...

Page 195: ...d interrupt status fw_long un_regs LINT_STAT_A int_status clear status check for mailbox interrupt if int_status LINT_STAT_MBOX0 mb0_msg fr_long un_regs MBOX0_A if int_status LINT_STAT_MBOX1 mb1_msg f...

Page 196: ...BOX1_A 0 fw_long un_regs MBOX2_A 0 fw_long un_regs MBOX3_A 0 tmp_status fr_long un_regs LINT_STAT_A read interrupt status fw_long un_regs LINT_STAT_A tmp_status clear status re enable MB0 ints lint_en...

Page 197: ...196 G VMIVME 7697 Product Manual enable Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 198: ...define SEC_LE 0x0000 slave endian conversion little endian define BERR_LATCH_EN 0x0004 buss error latch enable define BTO_EN 0x0008 bus timeout timer enable define BTO_16 0x0000 bus timeout 16 us defi...

Page 199: ...ed long pci_u1 unimplemented unsigned long pci_r1 0x02 reserved unsigned long pci_misc1 PCI config miscellaneous 1 reg unsigned long pci_u2 0x30 unimplemented unsigned long lsi0_ctl PCI slave image 0...

Page 200: ...PCI special cycle compare data reg unsigned long scyc_swp PCI special cycle swap data reg unsigned long lmisc PCI miscellaneous reg unsigned long slsi PCI special PCI slave image unsigned long l_cmder...

Page 201: ...g unsigned long urA reserved unsigned long dcpp DMA command packet pointer unsigned long urB reserved unsigned long dgcs DMA general control and status reg unsigned long d_llue DMA linked list update...

Page 202: ...r AM codes reg unsigned long urE 0x2bc reserved unsigned long vsi0_ctl VMEbus slave image 0 control reg unsigned long vsi0_bs VMEbus slave image 0 base address reg unsigned long vsi0_bd VMEbus slave i...

Page 203: ...rr VMEbus address error log unsigned long vsi4_ctl VMEbus slave image 4 control reg unsigned long vsi4_bs VMEbus slave image 4 base address reg unsigned long vsi4_bd VMEbus slave image 4 bound address...

Page 204: ...ellaneous 1 reg define LSI0_CTL_A 0x100 PCI slave image 0 control reg define LSI0_BS_A 0x104 PCI slave image 0 base address reg define LSI0_BD_A 0x108 PCI slave image 0 bound address reg define LSI0_T...

Page 205: ...ve image 5 control reg define LSI5_BS_A 0x1B8 PCI slave image 5 base address reg define LSI5_BD_A 0x1BC PCI slave image 5 bound address reg define LSI5_TO_A 0x1C0 PCI slave image 5 translation offset...

Page 206: ...Q4 define V5_STATID_A 0x334 VME interrupt status ID in IRQ5 define V6_STATID_A 0x338 VME interrupt status ID in IRQ6 define V7_STATID_A 0x33C VME interrupt status ID in IRQ7 define LINT_MAP2_A 0x340 P...

Page 207: ...Monitor Base Address define VRAI_CTL_A 0xF70 VMEbus register access image control reg define VRAI_BS_A 0xF74 VMEbus register access image base address define VCSR_CTL_A 0xF80 VMEbus CSR control reg d...

Page 208: ...cture typedef struct slave_window unsigned long win_ctl unsigned long win_bs unsigned long win_bd unsigned long win_to swin_config_t DMA command packet structure for dmas using linked lists typedef st...

Page 209: ...00040 R W parity error response define PCI_CSR_VGAPS 0x00000020 R VGA palette snoop define PCI_CSR_MWI_EN 0x00000010 R mem write and invalidate enable define PCI_CSR_SC 0x00000008 R special cycles def...

Page 210: ...fine LSI_CTL_EN 0x80000000 R W image enable define LSI_CTL_PWEN 0x40000000 R W posted write enable define LSI_CTL_VDW_08 0x00000000 R W VMEbus maximum data width D08 define LSI_CTL_VDW_16 0x00400000 R...

Page 211: ...dress MASK define LSI3_BS 0xFFFF0000 R W PCI slave image 3 base address MASK define LSI4_BS 0xFFFFF000 R W PCI slave image 4 base address MASK define LSI5_BS 0xFFFF0000 R W PCI slave image 5 base addr...

Page 212: ...ace define SCYC_CTL_DIS 0x00000000 R W special cycle disabled define SCYC_CTL_RMW 0x00000001 R W read modify write define SCYC_CTL_ADOH 0x00000002 R W address only define SCYC_CTL_RSVD 0x00000003 R W...

Page 213: ...indow timer 2048 us define LMISC_CWT_6 0x06000000 R W coupled window timer 4096 us slsi special PCI slave image define SLSI_EN 0x80000000 R W image enable define SLSI_PWEN 0x40000000 R W posted write...

Page 214: ...space reserved 1 define DCTL_VAS_R2 0x00040000 R W VMEbus address space reserved 2 define DCTL_VAS_R3 0x00050000 R W VMEbus address space reserved 3 define DCTL_VAS_U1 0x00060000 R W VMEbus address sp...

Page 215: ..._VON6 0x00500000 R W VME aligned DMA xfer cnt 4096 define DGCS_VON7 0x00600000 R W VME aligned DMA xfer cnt 8192 define DGCS_VON8 0x00700000 R W VME aligned DMA xfer cnt 16384 define DGCS_VOFF1 0x0000...

Page 216: ...ce updating list lint_en PCI interrupt enable register define LINT_EN_LM3 0x00800000 R W Location monitor 3 enable define LINT_EN_LM2 0x00400000 R W Location monitor 2 enable define LINT_EN_LM1 0x0020...

Page 217: ...BOX3 0x00080000 R W MAILBOX 3 received define LINT_STAT_MBOX2 0x00040000 R W MAILBOX 2 received define LINT_STAT_MBOX1 0x00020000 R W MAILBOX 1 received define LINT_STAT_MBOX0 0x00010000 R W MAILBOX 0...

Page 218: ...0x50000000 R W PCI int LINT 5 for VME IRQ7 define LINT_MAP0_VIRQ7_6 0x60000000 R W PCI int LINT 6 for VME IRQ7 define LINT_MAP0_VIRQ7_7 0x70000000 R W PCI int LINT 7 for VME IRQ7 define LINT_MAP0_VIRQ...

Page 219: ...0000 R W PCI int LINT 0 for VME IRQ4 define LINT_MAP0_VIRQ4_1 0x00010000 R W PCI int LINT 1 for VME IRQ4 define LINT_MAP0_VIRQ4_2 0x00020000 R W PCI int LINT 2 for VME IRQ4 define LINT_MAP0_VIRQ4_3 0x...

Page 220: ...W PCI int LINT 3 for VME IRQ2 define LINT_MAP0_VIRQ2_4 0x00000400 R W PCI int LINT 4 for VME IRQ2 define LINT_MAP0_VIRQ2_5 0x00000500 R W PCI int LINT 5 for VME IRQ2 define LINT_MAP0_VIRQ2_6 0x0000060...

Page 221: ...VOWN_6 0x00000006 R W PCI int LINT 6 for VME OWN define LINT_MAP0_VOWN_7 0x00000007 R W PCI int LINT 7 for VME OWN lint_map1 PCI interrupt map 1 register define LINT_MAP1_ACFAIL_0 0x00000000 R W PCI i...

Page 222: ...00000 R W PCI int LINT 0 for SW_INT define LINT_MAP1_SW_INT_1 0x00100000 R W PCI int LINT 1 for SW_INT define LINT_MAP1_SW_INT_2 0x00200000 R W PCI int LINT 2 for SW_INT define LINT_MAP1_SW_INT_3 0x00...

Page 223: ...efine LINT_MAP1_LERR_0 0x00000000 R W PCI int LINT 0 for LERR define LINT_MAP1_LERR_1 0x00000010 R W PCI int LINT 1 for LERR define LINT_MAP1_LERR_2 0x00000020 R W PCI int LINT 2 for LERR define LINT_...

Page 224: ...0x00001000 R W enable VMEbus int SW_IACK define VINT_EN_VERR 0x00000400 R W enable PCIbus int VERR define VINT_EN_LERR 0x00000200 R W enable PCIbus int LERR define VINT_EN_DMA 0x00000100 R W enable P...

Page 225: ...ne VINT_STAT_LINT6 0x00000040 R WC VMEbus int LINT6 define VINT_STAT_LINT5 0x00000020 R WC VMEbus int LINT5 define VINT_STAT_LINT4 0x00000010 R WC VMEbus int LINT4 define VINT_STAT_LINT3 0x00000008 R...

Page 226: ...x00500000 R W VME int 5 for LINT5 define VINT_MAP0_LINT5_6 0x00600000 R W VME int 6 for LINT5 define VINT_MAP0_LINT5_7 0x00700000 R W VME int 7 for LINT5 define VINT_MAP0_LINT4_D 0x00000000 R W VME in...

Page 227: ...R W VME int 1 for LINT1 define VINT_MAP0_LINT1_2 0x00000020 R W VME int 2 for LINT1 define VINT_MAP0_LINT1_3 0x00000030 R W VME int 3 for LINT1 define VINT_MAP0_LINT1_4 0x00000040 R W VME int 4 for LI...

Page 228: ...R define VINT_MAP1_VERR_3 0x00000300 R W VME int 3 for VERR define VINT_MAP1_VERR_4 0x00000400 R W VME int 4 for VERR define VINT_MAP1_VERR_5 0x00000500 R W VME int 5 for VERR define VINT_MAP1_VERR_6...

Page 229: ...ster 0xXXXXXX00 v4_statid R VIRQ4 STATUS ID register 0xXXXXXX00 v5_statid R VIRQ5 STATUS ID register 0xXXXXXX00 v6_statid R VIRQ6 STATUS ID register 0xXXXXXX00 v7_statid R VIRQ7 STATUS ID register 0xX...

Page 230: ...W PCI int LINT 6 for LOC MON2 define LINT_MAP2_LM2_7 0x07000000 R W PCI int LINT 7 for LOC MON2 define LINT_MAP2_LM1_0 0x00000000 R W PCI int LINT 0 for LOC MON1 define LINT_MAP2_LM1_1 0x00100000 R W...

Page 231: ...01000 R W PCI int LINT 1 for MAILBOX3 define LINT_MAP2_MB3_2 0x00002000 R W PCI int LINT 2 for MAILBOX3 define LINT_MAP2_MB3_3 0x00003000 R W PCI int LINT 3 for MAILBOX3 define LINT_MAP2_MB3_4 0x00004...

Page 232: ...W PCI int LINT 4 for MAILBOX1 define LINT_MAP2_MB1_5 0x00000050 R W PCI int LINT 5 for MAILBOX1 define LINT_MAP2_MB1_6 0x00000060 R W PCI int LINT 6 for MAILBOX1 define LINT_MAP2_MB1_7 0x00000070 R W...

Page 233: ...int VIRQ 7 for MAILBOX3 define VINT_MAP2_MB2_1 0x00000100 R W VME int VIRQ 1 for MAILBOX2 define VINT_MAP2_MB2_2 0x00000200 R W VME int VIRQ 2 for MAILBOX2 define VINT_MAP2_MB2_3 0x00000300 R W VME in...

Page 234: ...LBOX0 define VINT_MAP2_MB0_5 0x00000005 R W VME int VIRQ 5 for MAILBOX0 define VINT_MAP2_MB0_6 0x00000006 R W VME int VIRQ 6 for MAILBOX0 define VINT_MAP2_MB0_7 0x00000007 R W VME int VIRQ 7 for MAILB...

Page 235: ...AST_CTL_VRL_3 0x00C00000 R W VMEbus request level 3 define MAST_CTL_VRM_D 0x00000000 R W VMEbus request mode demand define MAST_CTL_VRM_F 0x00200000 R W VMEbus request mode fair define MAST_CTL_VREL_R...

Page 236: ...0x00800000 W software PCI reset define MISC_CTL_SW_SRST 0x00400000 W software VME sysrest define MISC_CTL_BI 0x00100000 R W universe in BI Mode define MISC_CTL_ENGBI 0x00080000 R W enable global BI in...

Page 237: ..._VAS_24 0x00010000 R W address space A24 define VSI_CTL_VAS_32 0x00020000 R W address space A32 define VSI_CTL_VAS_R1 0x00030000 R W address space reserved 1 define VSI_CTL_VAS_R2 0x00040000 R W addre...

Page 238: ...FF0000 R W VME slave image 3 offset MASK lm_ctl location monitor control define LM_CTL_EN 0x80000000 R W location monitor enable define LM_CTL_AM_D 0x00400000 R W location monitor AM DATA define LM_CT...

Page 239: ...CTL_EN 0x80000000 R image enable define VCSR_CTL_LAS_M 0x00000000 R W PCIbus memory space define VCSR_CTL_LAS_I 0x00000001 R W PCIbus I O space define VCSR_CTL_LAS_C 0x00000002 R W PCIbus configuratio...

Page 240: ...et register define VCSR_SET_RESET 0x80000000 R W board reset define VCSR_SET_SYSFAIL 0x40000000 R W VMEbus sysfail define VCSR_SET_FAIL 0x20000000 R board fail vcsr_bs VMEbus CSR base address register...

Page 241: ...M 0 0 0 0 define CLK_DATE 0x08 01 31 0 0 define CLK_MONTH 0x09 01 12 0 define CLK_YRS 0x0A 00 99 define WD_CMD 0x0B command register define WD_MSEC 0x0C milli second watchdog time define WD_SEC 0x0D s...

Page 242: ...r ID TWRUN C function prototypes void init_int void void restore_orig_int void void interrupt nmi_irq_rcvd void global variables unsigned long int_status FPTR wd_base void far interrupt old_nmi_vect v...

Page 243: ...BASE ADDRESS 0x24 in config space n exit 1 wd_base temp_dword 0xFFFFFFF0 extend_seg a20 1 set WatchDog Alarm Mask 1 deactivated and update with 0 time fw_byte wd_base WD_CMD WD_TE WD_WAM fw_byte wd_ba...

Page 244: ...tatus break delay 1 to_cnt while to_cnt if to_cnt printf Timed out waiting for interrupt n if int_status 1 printf ISR received n else printf ISR never entered n fw_byte wd_base 0x40 0x00 disable watch...

Page 245: ...atchdog alarm mask to 1 restore_orig_int a20 0 end main void do_exit int xcode exit xcode init_int purpose Using the interrupt assigned the original vector is saved and the vector to the new ISR is in...

Page 246: ...t clear bit 2 to enable NMI enable nmi outp 0x70 0x80 outp 0x70 0x00 enable init_int restore_orig_int purpose Using the interrupt assigned the original vector is restored and the programmable interrup...

Page 247: ...inp 0x61 0x0F nmidat 0x04 outp 0x61 nmidat set bit 2 to clear any previous condition setvect 2 old_nmi_vect enable restore_orig_int nmi_irq_rcvd purpose Interrupt service routine used to service nmi...

Page 248: ...d with 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to disable fw_byte wd_base WD_CMD WD_TE WD_WAM allow update with 0 time fw_byte wd_base WD_CMD WD_WAM set watchdog alarm mask to 1 rearm nmi nm...

Page 249: ...D_7697 0x114A Vendor ID void main int argc char argv int test_int unsigned long temp_dword unsigned char bus dev_func FPTR wd_base try to locate the 7697 device on the PCI bus test_int find_pci_device...

Page 250: ...h 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to disable fw_byte wd_base WD_CMD WD_TE WD_WAM allow update with 0 time fw_byte wd_base WD_CMD WD_WAM set watchdog alarm mask to 1 Jumper E18 must b...

Page 251: ...AM fw_byte wd_base WD_MSEC 0 load with 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to disable fw_byte wd_base WD_CMD WD_TE WD_WAM allow update with 0 time fw_byte wd_base WD_CMD WD_WAM set watch...

Page 252: ...ce ID define VID_7697 0x114A Vendor ID void main int argc char argv int test_int index unsigned long temp_dword unsigned char bus dev_func FPTR wd_base try to locate the 7697 device on the PCI bus tes...

Page 253: ...e WD_MSEC 0 load with 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to disable fw_byte wd_base WD_CMD WD_TE WD_WAM allow update with 0 time fw_byte wd_base WD_CMD WD_WAM set watchdog alarm mask to...

Page 254: ...time fw_byte wd_base WD_CMD WD_TE WD_WAM fw_byte wd_base WD_MSEC 0 load with 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to disable fw_byte wd_base WD_CMD WD_TE WD_WAM allow update with 0 time f...

Page 255: ...vice ID define VID_7697 0x114A Vendor ID global variables unsigned char bus dev_func FPTR wd_base FPTR sys_base void main int argc char argv int test_int unsigned long temp_dword sys_base 0xD800E try...

Page 256: ...nd_seg a20 1 set WatchDog Alarm Mask 1 deactivated and update with 0 time fw_byte wd_base WD_CMD WD_TE WD_WAM fw_byte wd_base WD_MSEC 0 load with 0 to disable fw_byte wd_base WD_SEC 0 load with 0 to d...

Page 257: ...00 disable watchdog in EPLD set WatchDog Alarm Mask 1 deactivated and update with 0 time fw_byte wd_base WD_CMD WD_TE WD_WAM fw_byte wd_base WD_MSEC 0 load with 0 to disable fw_byte wd_base WD_SEC 0 l...

Page 258: ...152 E Ethernet controller 156 Digital Semiconductor s 21143 controller 56 interrupt logic 54 LED definition 42 Windows 95 setup 104 Windows for Workgroups V3 11 102 Windows NT Version 4 0 108 Expansi...

Page 259: ...ISA bridge 156 PCI Mezzanine Card PMC 41 PIIX4 156 power supply load 141 Power on Self Test 148 Primary Master Slave 113 programmable time 46 protected mode 45 49 R real mode 45 49 real time clock 46...

Page 260: ...try sets 63 Mode Register Values 71 Width Bit Field 70 Timer 2 width 70 Timer Block Diagram 62 timer control 60 U unpacking procedures 31 Upper Counter 60 USB interrupt mapping 156 USB port connector...

Page 261: ...VMIVME 7697 Product Manual 260 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 262: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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Summary of Contents for VMIVME-7697

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VMIC VMIVME-7697, Product Manual, Page: 1 / 262

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Summary of Contents for VMIVME-7697

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