VMIC VMICPCI-7715 Product Manual Download Page 1

Page: 1 / 192

12090 South Memorial Parkway

Huntsville, Alabama 35803-3308, USA

(256) 880-0444

(800) 322-3616

Fax: (256) 882-0859

VMICPCI-7715

Single Board, All Rear I/O Pentium III

Socket 370

Processor-Based CompactPCI SBC

Product Manual

500-657715-000 Rev. A

Summary of Contents for VMICPCI-7715

Page 1: ...l Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 VMICPCI 7715 Single Board All Rear I O Pentium III Socket 370 Processor Based CompactPCI SBC Product Manual 5...

Page 2: ......

Page 3: ...nk RTnet Soft Logic Link SRTbus TESTCAL The Next Generation PLC The PLC Connection TURBOMODULE UCLIO UIOD UPLC Visual Soft Logic Control ler VMEaccess VMEbus Access VMEmanager VMEmonitor VMEnet VMEnet...

Page 4: ......

Page 5: ...ures 26 VMICPCI 7715 Product Options 26 Chapter 2 Installation and Setup 29 Unpacking Procedures 29 Hardware Setup 30 Installation 34 BIOS Setup 35 PMC Expansion Site Connectors 35 Chapter 3 PC AT Fun...

Page 6: ...isters 57 Watchdog Alarm Registers 58 Command Register 58 Timers 60 General 60 Timer Interrupt Status 60 Clearing the Interrupt 61 Timer Programming 61 Architecture 61 Writing 63 Reading 65 Mode Defin...

Page 7: ...Drive A 91 Floppy Drive B 91 Primary Master Slave 91 Secondary Master 92 Keyboard Features 92 NumLock 92 Key Click 92 Keyboard Auto Repeat Rate Chars Sec 92 Keyboard Auto Repeat Delay sec 93 Keyboard...

Page 8: ...es 101 Appendix D LANWorks BIOS 103 Boot Menus 104 First Boot Menu 104 Boot Menu 104 BIOS Features Setup 106 RPL 106 TCP IP 106 Netware 107 PXE 107 Appendix E Device Configuration I O and Interrupt Co...

Page 9: ...LE PCI C 137 FILE PCI H 140 FILE UNIVERSE H 141 Directory Smbus 166 FILE Pci h 166 FILE SCAN H 168 Directory SRAM 169 File T_SRAM C 169 Directory Timers 172 File CPU H 172 File PCI H 174 File PCI C 17...

Page 10: ...10...

Page 11: ...s 60 Figure 4 3 Timer Interrupt Status Register 61 Figure 4 4 Clearing the Timer Interrupt Status Register 61 Figure 4 5 82C54 Diagram 62 Figure 4 6 Internal Timer Diagram 63 Figure A 1 VMICPCI 7715 C...

Page 12: ...12...

Page 13: ...CI 7715 Interface Memory Address Map 39 Table 3 2 VMICPCI 7715 I O Address Map 40 Table 3 3 PC AT Hardware Interrupt Line Assignments 42 Table 3 4 PC AT Interrupt Vector Table 43 Table 3 5 NMI Registe...

Page 14: ...Address 70 Table 4 15 LSB Control Bytes 70 Table A 1 PMC J7 Connector Pinout 79 Table A 2 PMC J8 Connector Pinout 80 Table A 3 PMC J6 Connector Pinout 81 Table E 1 ISA Device Mapping Configuration 114...

Page 15: ...on self test then boots up Windows 98 SE Windows NT or any other PC AT compatible operating system The PC AT mode of the VMICPCI 7715 is discussed in Chapter 3 of this manual The VMICPCI 7715 also ope...

Page 16: ...vides information relative to the care and maintenance of the unit Appendix A Connector Pinouts illustrates and defines the connectors included in the unit s I O ports Appendix B Phoenix BIOS describe...

Page 17: ...5052 8119 408 765 8080 www intel com Intel 21154 PCI to PCI Bridge Intel Corporation 2200 Mission College Blvd P O Box 58119 Santa Clara CA 95052 8119 PCI Special Interest Group P O Box 14070 Portland...

Page 18: ...4070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX SMC FDC37C67X Enhanced Super I O Controller SMC Component Products Division 300 Kennedy Dr Hauppauge NY 11788 516 43...

Page 19: ...0 from IEEE Standards Department Copyrights and Permissions 445 Hoes Lanes P O Box 1331 Piscataway NJ 08855 1331 USA PMC Specification P1386 1 Draft 2 0 from IEEE Standards Department Copyrights and P...

Page 20: ...ment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maint...

Page 21: ...onnection to the frame chassis of the equipment which normally includes all exposed metal structures Alternating current power line Direct current power line Alternating or direct current power line S...

Page 22: ...VMICPCI 7612 Product Manual 22...

Page 23: ...ons up to 1280x1024x256 colors Battery backed clock calendar On board support for a keyboard and mouse speaker output Ultra IDE hard drive and floppy drive through CPCI J5 On board Ethernet controller...

Page 24: ...ugh rear I O J5 Two USB Ports Through rear I O J5 AT Style Keyboard Mouse Controller Through rear I O J5 Super VGA Video Controller with 4 Mbyte SGRAM Through rear I O J4 Ethernet 10BaseT 100BaseTx No...

Page 25: ...C T 69030 Intel 21154 Intel 82559ER 82443BX SUPER I O with RTC SMC FDC37C67X DiskOnChip Flash BIOS Watchdog Timer DS1384 North Bridge System South Bridge SVGA COM Port 2 PMC Site Hard Processor 10Bas...

Page 26: ...ad data buffering upstream and 72 bytes of read data buffering downstream Provides concurrent primary and secondary bus operation to isolate traffic Provides enhanced address decoding Includes address...

Page 27: ...27 CompactPCI Features 1...

Page 28: ...28 1 VMICPCI 7715 Product Manual...

Page 29: ...ing shipment All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service along with a request for advice concerning the disposition of...

Page 30: ...em operation and shipped with factory installed configurable jumpers The physical location of the jumpers for the SBC are illustrated in Figure 2 1 on page 31 The definitions of the SBC board jumpers...

Page 31: ...31 Hardware Setup 2 Figure 2 1 VMICPCI 7715 Board Jumper Locations Located On Reverse Side...

Page 32: ...t E24 3 Power up the unit 4 Turn off the power to the unit and remove jumper E24 When power is re applied to the unit the CMOS will be cleared Table 2 1 Board Connectors Connector Function CPCI J5 PS...

Page 33: ...OS Battery Enable User Configurable Jumper E23 Jumper Position CMOS Battery Disabled Out CMOS Battery Enabled In Table 2 6 Watchdog Battery Enable User Configurable Jumper E22 Jumper Position Watchdog...

Page 34: ...signated system slot of the CompactPCI backplane NOTE The VMICPCI 7715 requires forced air cooling It is advisable to install blank panels over any exposed slots This will allow for better air flow ov...

Page 35: ...5 is shipped from the factory with no hard drives configured in CMOS The BIOS Setup program must be run to configure the specific drives attached Details of the VMICPCI 7715 BIOS setup program are inc...

Page 36: ...36 2 VMICPCI 7715 Product Manual...

Page 37: ...ete Pentium III processor based Single Board Computer SBC The design includes a high speed microprocessor with current technology memory Because the design is PC AT compatible it retains standard PC m...

Page 38: ...mory The VMICPCI 7715 provides 512 Mbytes of Synchronous DRAM SDRAM as on board system memory Memory can be accessed as bytes words or longwords All RAM on the VMICPCI 7715 is dual ported to the Compa...

Page 39: ...dress space which is accessible as bytes words or longwords Table 3 1 VMICPCI 7715 Interface Memory Address Map MODE MEMORY ADDRESS RANGE SIZE DESCRIPTION PROTECTED MODE FFFF 0000 FFFF FFFF 64 Kbyte R...

Page 40: ...ble 3 2 Table 3 2 VMICPCI 7715 I O Address Map I O ADDRESS RANGE SIZE IN BYTES HW DEVICE PC AT FUNCTION 000 00F 16 DMA Controller 1 Intel 8237A Compatible 010 01F 16 Reserved 020 021 2 Master Interrup...

Page 41: ...ed 2E8 2EE 7 UART COM4 Serial I O 2EF 2F7 9 User I O 2F8 2FE 7 Super I O Chip COM2 Serial I O 16550 Compatible 2FF 36F 113 Reserved 370 377 8 Super I O Chip Secondary Floppy Disk Controller 378 37F 8...

Page 42: ...d from IRQ0 to IRQ7 at the PIC The IBM PC AT computer added eight more IRQx lines numbered IRQ8 to IRQ15 by cascading a second slave PIC into the original master PIC IRQ2 at the master PIC was committ...

Page 43: ...enabled in BIOS Setup 03 3 Debug Breakpoint Same as Real Mode 04 4 ALU Overflow Same as Real Mode 05 5 Print Screen Array Bounds Check 06 6 Invalid OpCode 07 7 Device Not Available 08 8 IRQ0 Timer Tic...

Page 44: ...ontrol Same as Real Mode 1D 29 Video Parameter Table Pntr Same as Real Mode 1E 30 Floppy Parm Table Pntr Same as Real Mode 1F 31 Video Graphics Table Pntr Same as Real Mode 20 32 DOS Terminate Program...

Page 45: ...61 66 97 102 User Available Same as Real Mode 67 70 103 112 Reserved by DOS Same as Real Mode 71 113 IRQ9 USB 72 114 IRQ10 Assigned by BIOS 73 115 IRQ11 Assigned by BIOS 74 116 IRQ12 Mouse 75 117 IRQ1...

Page 46: ...nd the PCI expansion site Any function on a multifunction device can be connected to any of the INTx lines The Interrupt Pin register defines which INTx line the function uses to request an interrupt...

Page 47: ...rupt Logic Controller 8259 MASTER PORTS 020 021 IRQ0 IRQ1 IRQ2 IRQ4 IRQ5 IRQ7 IRQ8 IRQ9 IRQ10 IRQ12 PCI to PCI INTA PCI INTERRUPT IRQ6 IRQ3 IRQ11 IRQ13 IRQ14 IRQ15 CPU INTR CONNECTIONS MAPPED BY BIOS...

Page 48: ...ports VESA high resolution and extended video modes Table 3 6 shows the graphics video modes supported by the VMICPCI 7715 Not all SVGA monitors support resolutions and refresh rates beyond 640 x 480...

Page 49: ...supports 10BaseT and 100BaseTx Ethernet 10BaseT A network based on the 10BaseT standard uses unshielded twisted pair cables providing an economical solution to networking by allowing the use of exist...

Page 50: ...50 3 VMICPCI 7715 Product Manual...

Page 51: ...ible CPU The unit provides three software controlled general purpose timers in addition to a programmable Watchdog Timer The VMICPCI 7715 also provides a bootable DiskOnChip and 32 Kbytes of Nonvolati...

Page 52: ...formatted with the System files in order for it to be a bootable drive See Configuring the DiskOnChip as the Boot Device below 2 To install the DiskOnChip as a logical drive on a system with a hard d...

Page 53: ...nChip with Other Operating Systems If the VMICPCI 7715 is to be used with a DiskOnChip running an operating system other than DOS the user should access the MSystems website at www m sys com for infor...

Page 54: ...tween 0 01 and 99 99 seconds NOTE The Watchdog Timer Interrupt output must be set to Level Mode see Watchdog Command Register Bit 4 to use this option In addition the Watchdog Alarm is connected via a...

Page 55: ...ata in binary The Watchdog Alarm Registers are Registers C and D and information stored in these registers is in BCD Table 4 1 Watchdog Registers Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B...

Page 56: ...sed as the AM PM bit For AM Bit 5 is set to zero 0 and for PM Bit 5 is set to one 1 The total range of this register in the 12 hour format is 01 AM to 12 AM and 01 PM to 12 PM When Register 4 is in 24...

Page 57: ...ilar to Register 2 4 and 6 respectively Bit 7 of Registers 3 5 and 7 is a mask bit The mask bits when active logic one 1 disable the use of the particular Time of Day Alarm register in the determinati...

Page 58: ...g zeroes to Registers C and D will disable the Watchdog Alarm feature Command Register Register B is the Command Register Within this register are mask bits control bits and flag bits The following pa...

Page 59: ...nterrupt occurs This bit is reset when any of the Watchdog Alarm registers are accessed When the Interrupt Output is set to Pulse Mode see Bit 4 Interrupt Pulse Mode or Level Mode the flag will be set...

Page 60: ...d in the Timer Interrupt Status section below Timer Interrupt Status A single interrupt IRQ5 is used by all three Timers A Timer Interrupt Status register is provided in order to determine which Timer...

Page 61: ...T IRQ5 Refer to Appendix D for an example of using the 82C54 timers Timer Programming Architecture The VMICPCI 7715 Timers are mapped in I O address space starting at 500 See Table 4 3 The Timers cons...

Page 62: ...rol Word Register and the present state of the output and load count flag The Status Word is available via the Read Back command see the Reading section on page 65 The Timer is labeled TE Timer Elemen...

Page 63: ...e directly written to by the user the count is written to the TR registers then latched to the TE Figure 4 6 Internal Timer Diagram Writing The Timers are programmed by first writing a Control Word an...

Page 64: ...e 4 6 RW Read Write RW1 RW0 Description 0 0 Timer Latch Command see Reading section 0 1 Read Write least significant byte only 1 0 Read Write most significant byte only 1 1 Read Write least significan...

Page 65: ...y without affecting the timing in process Like a Control Word the Timer Latch Command is written to the Control Word Register I O Address 503 see Table 4 3 The Select Timer bits ST1 ST0 see Table 4 5...

Page 66: ...hed count will be held until it is read The Read Back command can also be used to latch the timer status by setting the Status bit 0 and selecting the Timers Status of a Timer is accessed by a read fr...

Page 67: ...by setting both the Count bit D5 and Status bit D4 to zero 0 in the Read Back command If this technique is used the first read operation of the Timer will return the status while the next one or two...

Page 68: ...as a divide by N counter Once a Control Word and an initial count are written to the Timer the initial count is loaded on the next Clock cycle When the count decrements to 1 an interrupt is generated...

Page 69: ...0 to DFFFF The lower 16 bytes D8000 to D800F are dedicated to the Watchdog Timer and the Board ID Register and are unavailable for SRAM use See the Watchdog Timer section The non volatile SRAM can be...

Page 70: ...Smbus multiplexer address The two LSB s of the control byte determine which connector the Smbus is directed toward refer to Table 4 15 Once the appropriate control word is written to the multiplexer t...

Page 71: ...No components or adjacent boards were disturbed when inserting or removing the board from the chassis 8 Quality of cables and I O connections If products must be returned obtain a RMA Return Material...

Page 72: ...72 5 VMICPCI 7715 Product Manual...

Page 73: ...tor Pinout 79 PMC J8 Connector Pinout 80 PMC J6 Connector Pinout 81 Introduction The VMICPCI 7715 PC AT Compatible CompactPCI Controller has all I O distributed through CompactPCI J2 J4 and J5 connect...

Page 74: ...74 A VMICPCI 7715 Product Manual Figure A 1 VMICPCI 7715 Connector Locations Located On Reverse Side...

Page 75: ...CK64 N C 23 CPCI_3 3 C_AD 4 C_AD 3 5 V C_AD 2 GND 22 C_AD 7 GND CPCI_3 3 C_AD 6 C_AD 5 N C 21 CPCI_3 3 C_AD 9 C_AD 8 GND C_C BE0 GND 20 C_AD 12 GND CPCI_VIO C_AD 11 C_AD 10 N C 19 CPCI_3 3 C_AD 15 C_A...

Page 76: ...N C 18 N C N C N C GND N C GND 17 N C GND C PRST C_REQ6 C_GNT6 N C 16 N C N C C_DEG GND N C GND 15 N C GND C_FAL C_REQ5 C_GNT5 N C 14 N C N C N C GND N C GND 13 N C GND CPCI_VIO N C N C N C 12 N C N...

Page 77: ...I O_22 PMC_I O_23 PMC_I O_24 PMC_I O_25 20 PMC_I O_26 PMC_I O_27 PMC_I O_28 PMC_I O_29 PMC_I O_30 19 PMC_I O_31 PMC_I O_32 PMC_I O_33 PMC_I O_34 PMC_I O_35 18 PMC_I O_36 PMC_I O_37 PMC_I O_38 PMC_I O_...

Page 78: ...ETHERNET_TERM ETHERNET_TERM ETH_ACTLED ETHERNET_TERM ETHERNET_TERM 16 ETH_TX ETH_TX ETH_100BT ETH_RX ETH_RX 15 GND GND ETH_10BT GND GND 14 SERIAL0_DTR SERIAL0_RI GND SERIAL0_CTS SERIAL0_RTS 13 SERIAL...

Page 79: ...ide Left Side Right Side Pin Name Pin Name Pin Name Pin Name 1 GND 2 12 33 FRAME 34 GND 3 GND 4 INTD 35 GND 36 IRDY 5 INTA 6 INTB 37 DEVSEL 38 5 V 7 BMODE1A 8 5 V 39 GND 40 LOCK 9 INTC 10 NC 41 SDONE...

Page 80: ...Y 36 3 3 V 5 5 V 6 GND 37 GND 38 STOP 7 GND 8 NC 39 PERR 40 GND 9 NC 10 NC 41 3 3 V 42 SERR 11 PRSNT2 12 3 3 V 43 C BE1 44 GND 13 RST 14 GND 45 AD 14 46 AD 13 15 3 3 V 16 GND 47 GND 48 AD 10 17 NC 18...

Page 81: ...C_I O_41 42 PMC_I O_42 11 PMC_I O_11 12 PMC_I O_12 43 PMC_I O_43 44 PMC_I O_44 13 PMC_I O_13 14 PMC_I O_14 45 PMC_I O_45 46 PMC_I O_46 15 PMC_I O_15 16 PMC_I O_16 47 PMC_I O_47 48 PMC_I O_48 17 PMC_I...

Page 82: ...82 A VMICPCI 7715 Product Manual...

Page 83: ...timize performance of each of these PCI based subsystems the VMICPCI 7715 is provided with software drivers compatible with DOS Windows 2000 and Windows NT operating systems The following paragraphs p...

Page 84: ...ts the Found New Hardware wizard will appear Click Next 14 Insert disk 320 500076 003 15 Select Search for A Suitable Driver For My Device and click Next 16 On the Locate Drivers Files select Floppy D...

Page 85: ...continue 10 The Digital Signature Not Found box indicates this is not a Microsoft driver Select Yes to continue 11 After the files have been coped select Finish to complete the driver installation 12...

Page 86: ...displayed list click Next 10 Select the NetBEUI Protocol only click Next 11 Click Next to install selected components 12 Click Next to start the network connection 13 Step through the remaining screen...

Page 87: ...displayed in the Change Display window Click OK 26 Proceed as directed removing the driver disk from the floppy drive Restart the computer to activate the new settings When the system reboots the Inva...

Page 88: ...88 B VMICPCI 7715 Product Manual...

Page 89: ...ion such as floppy drive configuration or system memory The parameters shown throughout this section are the default values Help Window The help window on the right side of each menu displays the help...

Page 90: ...ce bar to step through the available choices or type in the information Setting The Date Press the left or right arrow key to move the cursor to the desired field month day year Press the space bar to...

Page 91: ...a second floppy drive The default is Disabled Primary Master Slave The VMICPCI 7715 is capable of utilizing one IDE hard disk drive on the Primary Master bus The default setting is Auto The Primary Sl...

Page 92: ...ption enables or disables the Keyboard Auto Repeat Rate and Delay settings When disabled the values in the Typematic Rate and Delay are ignored The default is Disabled Keyboard Auto Repeat Rate Chars...

Page 93: ...s the total amount of memory installed in the system in Kbytes Extended Memory The Extended Memory field is for informational purposes only and cannot be modified by the user This field displays the t...

Page 94: ...cts the type of console to be used The options are PC ANSI or VT100 The default is PC ANSI Flow Control Enables or disables Flow Control The options are No Flow Control XON XOFF or CTS RTS The default...

Page 95: ...uests data the system transfers the requested data from the main DRAM into the cache memory where it is stored until processed by the CPU The default is Enabled 3KRHQL 6HWXS 8WLOLW 0DLQ 9 1 3RZHU RRW...

Page 96: ...VDEOHG LVDEOHG LVDEOHG LVDEOHG HOS 6HOHFW WHP KDQJH 9DOXHV 6HWXS HIDXOWV 6 LW 6HOHFW 0HQX QWHU 6HOHFW 6XE 0HQX 6DYH DQG LW 3KRHQL 6HWXS 8WLOLW 9 1 WHP 6SHFLILF HOS 2 HYLFH RQILJXUDWLRQ RQILJXUH VHULDO...

Page 97: ...ult is Primary Advanced Chipset Control Selecting Advanced Chipset Control opens the menu below Use this menu to change the values in the chipset register for optimizing your system s performance Grap...

Page 98: ...conventional memory gap starting at 512kB or an extended memory gap starting at 15MB will be created in system RAM ECC Config If all memory in the system supports ECC x72 this selection selects from...

Page 99: ...LPXP 3HUIRUPDQFH FRQVHUYHV SRZHU EXW DOORZV JUHDWHVW V VWHP SHUIRUPDQFH 7R DOWHU WKHVH VHWWLQJV FKRRVH XVWRPL HG 7R WXUQ RII SRZHU PDQDJHPHQW FKRRVH LVDEOHG 0DQXDO 38 ORFN 7KURWWOLQJ LVDEOHG 38 7KURW...

Page 100: ...ice and pressing Shift 1 Enter expands or collapses devices with a or next to them 3KRHQL 6HWXS 8WLOLW 0DLQ GYDQFHG 3RZHU RRW LW WHP 6SHFLILF HOS LVNHWWH ULYH DUG ULYH H V XVHG WR YLHZ RU FRQILJXUH GH...

Page 101: ...arding any changes to CMOS Load Setup Defaults Load System defaults as defined at the factory Discard Changes Discard any changes without exiting the Setup program Save Changes Save any changes made w...

Page 102: ...102 C VMICPCI 7715 Product Manual...

Page 103: ...us 104 BIOS Features Setup 106 Introduction The VMICPCI 7715 includes a LANWorks option which allows the VMICPCI 7715 to be booted from a network This appendix describes the procedures to enable this...

Page 104: ...t menu Using the arrow keys highlight Managed PC Boot Agent MBA and press the Enter key to continue with the system boot Boot Menu The second method of enabling the LANWorks BIOS option is to press th...

Page 105: ...QWHU H SDQGV RU FROODSVHV GHYLFHV ZLWK D RU WUO QWHU H SDQGV DOO 6KLIW HQDEOHV RU GLVDEOHV D GHYLFH DQG PRYHV WKH GHYLFH XS RU GRZQ Q PD PRYH UHPRYDEOH GHYLFH EHWZHHQ DUG LVN RU 5HPRYDEOH LVN G UHPRY...

Page 106: ...WLRQ RRW 0HWKRG 53 RQILJ 0HVVDJH QDEOHG 0HVVDJH 7LPHRXW 6HFRQGV RRW IDLOXUH 3URPSW DLW IRU NH RRW DLOXUH 1H W 6 GHYLFH 8VH FXUVRU NH V WR HGLW 8S RZQ FKDQJH ILHOG HIW 5LJKW FKDQJH YDOXH 6 WR TXLW UHVW...

Page 107: ...XW 6HFRQGV RRW IDLOXUH 3URPSW DLW IRU NH RRW DLOXUH 1H W 6 GHYLFH 8VH FXUVRU NH V WR HGLW 8S RZQ FKDQJH ILHOG HIW 5LJKW FKDQJH YDOXH 6 WR TXLW UHVWRUH SUHYLRXV VHWWLQJV WR VDYH 0DQDJHG 3 RRW JHQW 0 Y...

Page 108: ...108 D VMICPCI 7715 Product Manual...

Page 109: ...the VMICPCI 7715 is unique in that the BIOS cannot be removed it must be used in the initial boot cycle A custom application like a revised operating system for example can only begin to operate after...

Page 110: ...which the user must be familiar in order to override the initial BIOS configuration These areas include the device addresses and the device interrupts This appendix reviews the details of these addre...

Page 111: ...69030 Intel 21154 Intel 82559ER 82443BX SUPER I O with RTC SMC FDC37C67X DiskOnChip Flash BIOS Watchdog Timer DS1384 North Bridge System South Bridge SVGA COM Port 2 PMC Site Hard Processor 10BaseT 1...

Page 112: ...or PIIX4E 2200 Mission College Blvd P O Box 58119 Santa Clara CA 95052 8119 4 Intel 82559 10 100 Mb s Ethernet LAN Controller Intel Corporation www intel com 5 Intel 69030 Technical Reference Manual I...

Page 113: ...eping Controller Dallas Semiconductor 4461 South Beltwood Pwky Dallas TX 75244 3292 10 IEEE P1386 PMC Specification The Institute of Electrical and Electronics Engineers Inc 345 East 47th St New York...

Page 114: ...rupts are mapped to standard interrupt control registers However all of the ISA devices with the exception of the real time clock keyboard and programmable timer are relocatable to almost anywhere wit...

Page 115: ...Specification for complete details on the configuration address space PCI bus targets are required to implement Base Address registers in configuration address space to access internal registers or f...

Page 116: ...t mapping is illustrated in Figure E 2 on page 117 within the PCI to ISA Bridge PIIX4E 82371EB section of the diagram To maintain backward compatibility with PC XT systems IBM chose to use the new IRQ...

Page 117: ...U CONNECTIONS MAPPED BY BIOS PMC Site BRIDGE C P C b u s Timer Keybd Com 2 Com 1 GP Floppy Control Interrupt 8 15 N A Real Tm Clock Mouse Math AT N A Hard Drv NA NA Coproc PIRQ0 PIRQ1 PIRQ2 PIRQ3 USB...

Page 118: ...ID SELECT DEVICE PCI INTERRUPT MOTHER BOARD PCI INTERRUPT MAPPER DATA BOOK REF REVISION ID CompactPCI Bridge Intel 81154 0x1011 0x0026 AD 19 N A N A 3 N A PCI Expansion Site N A Board Specific Board...

Page 119: ...d applications These files are provided to the VMICPCI 7715 user on disk 320 500076 007 Sample Application C Code for the VMICPCI 7715 included in the distribution disk set Because of the wide variety...

Page 120: ...nclude pci h include universe h include cpu h define PCI_BASE16 0x10000000 PCI BASE for A16 define VME_16_RA 0x0000C000 VME BASE for A16 REG ACCESS define IRQ9 0x71 Int No for hardware int 9 define IR...

Page 121: ...test_int find_pci_device UNIVERSE_DID UNIVERSE_VID 0 bus dev_func if test_int SUCCESSFUL test_int read_configuration_area READ_CONFIG_DWORD bus dev_func 0x10 temp_dword if test_int SUCCESSFUL un_regs...

Page 122: ..._VAS_16 enable VME with master slave set for big endian and time out 64 us fw_word CPUREGS VME_EN MEC_BE SEC_BE BYPASS_EN BTO_64 BTO_EN place additional code here do_exit 0 end main void do_exit int x...

Page 123: ...nterrupt controller pic2_org inp 0xa1 0xFF slave mask bits switch int_line case 0x9 old_vect getvect IRQ9 save vector for IRQ 09 setvect IRQ9 irq_rcvd enable interrupt 9 outp 0xa1 pic2_org 0xFD break...

Page 124: ...7F break end switch fw_long un_regs LINT_STAT_A 0xFFF7FF clear any previous status bits fw_long un_regs LINT_MAP0_A 0 map all VME ints to lint 0 INTA fw_long un_regs LINT_MAP1_A 0 map all ERR STAT int...

Page 125: ...vect break case 0xb setvect IRQB old_vect break case 0xc setvect IRQC old_vect break case 0xd setvect IRQD old_vect break case 0xe setvect IRQE old_vect break case 0xf setvect IRQF old_vect break end...

Page 126: ...X2 mb2_msg fr_long un_regs MBOX2_A if int_status LINT_STAT_MBOX3 mb3_msg fr_long un_regs MBOX3_A disable MB ints lint_enable fr_long un_regs LINT_EN_A lint_enable LINT_EN_MBOX3 LINT_EN_MBOX2 LINT_EN_M...

Page 127: ...127 Directory CPU F outp 0x20 0x20 Master end of irq command outp 0xa0 0x20 Slave end of irq command asm 386P pop ebx pop eax enable...

Page 128: ...ine SEC_BE 0x0002 slave endian conversion big endian define SEC_LE 0x0000 slave endian conversion little endian define BERR_LATCH_EN 0x0004 buss error latch enable define BTO_EN 0x0008 bus timeout tim...

Page 129: ...0xA0 define INBA20 0x60 define INBA20ON 0xDF define INBA20OFF 0xDD macro to clear keyboard port define kx while inp KB_PORT 2 define local Global Descriptor Table GDT pointer structure static struct f...

Page 130: ...rupts are enabled by this call void extend_seg void compute linear address and limit of GDT gdtptr linear_add seg_to_linear void far GDT gdtptr limit 15 disable regular interrupts disable disable NMI...

Page 131: ...hort nxt nxt asm 386P mov bx 8 mov gs bx mov es bx and al 0xfe mov cr0 eax int fr_byte FPTR adr int d asm 386P xor ax ax zero gs mov gs ax mov eax adr mov al byte ptr gs eax mov d ax return d int fr_w...

Page 132: ...ptr gs eax mov d eax return d void fw_byte FPTR a int d asm 386P xor ax ax zero gs mov gs ax mov eax a mov bx d mov byte ptr gs eax bl void fw_word FPTR a int d asm 386P xor ax ax zero gs mov gs ax m...

Page 133: ...rd ptr es edi dword ptr gs esi pop es give back es flat move word void fmw_string FPTR d FPTR s long n asm 386P have to use ES for string move push es save es xor ax ax zero gs mov gs ax mov es ax mov...

Page 134: ...VMICPCI 7715 Product Manual mov edi d This is the destination pointer mov esi s This is the source pointer mov ecx n This is the number of bytes rep movs byte ptr es edi byte ptr gs esi pop es give ba...

Page 135: ...r to GDT struct fword unsigned int limit unsigned long linear_add convert segmented address to linear address define seg_to_linear fp FPTR FP_SEG fp 4 FP_OFF fp flat memory function prototypes void a2...

Page 136: ...136 F VMICPCI 7715 Product Manual void fmw_string FPTR FPTR long flat move word void fmb_string FPTR FPTR long flat move byte...

Page 137: ...x flags _CX device_id _DX vendor_id _SI index _AH PCI_FUNCTION_ID _AL FIND_PCI_DEVICE geninterrupt 0x1a ax _AX bx _BX flags _FLAGS if flags CARRY_FLAG 0 ret_status HIGH_BYTE ax if ret_status SUCCESSFU...

Page 138: ...0 ret_status HIGH_BYTE ax if ret_status SUCCESSFUL data ecx else ret_status NOT_SUCCESSFUL return ret_status int write_configuration_area unsigned char function unsigned char bus_number unsigned char...

Page 139: ...ret_status HIGH_BYTE ax else ret_status NOT_SUCCESSFUL return ret_status void outpd unsigned short port unsigned long value _DX port _EAX value __emit__ 0x66 0xEF unsigned long inpd unsigned short por...

Page 140: ...s define SUCCESSFUL 0x00 define NOT_SUCCESSFUL 0x01 Prototypes int find_pci_device unsigned short device_id unsigned short vendor_id unsigned short index unsigned char bus_number unsigned char device_...

Page 141: ...ess reg unsigned long lsi0_bd PCI slave image 0 bound address reg unsigned long lsi0_to PCI slave image 0 translation offset reg unsigned long ur0 reserved unsigned long lsi1_ctl PCI slave image 1 con...

Page 142: ...t reg unsigned long ur6 reserved unsigned long lsi6_ctl PCI slave image 6 control reg unsigned long lsi6_bs PCI slave image 6 base address reg unsigned long lsi6_bd PCI slave image 6 bound address reg...

Page 143: ...ster control reg unsigned long misc_ctl miscellaneous control reg unsigned long misc_stat miscellaneous status reg unsigned long user_am user AM codes reg unsigned long urE 0x2bc reserved unsigned lon...

Page 144: ...mage 5 bound address reg unsigned long vsi5_to VMEbus slave image 5 translation offset unsigned long urM reserved unsigned long vsi6_ctl VMEbus slave image 6 control reg unsigned long vsi6_bs VMEbus s...

Page 145: ...17C PCI special cycle compare data reg define SCYC_SWP_A 0x180 PCI special cycle swap data reg define LMISC_A 0x184 PCI miscellaneous reg define SLSI_A 0x188 PCI special PCI slave image define L_CMDER...

Page 146: ...rrupt status ID in IRQ7 define LINT_MAP2_A 0x340 PCI interrupt map2 define VINT_MAP2_A 0x344 VME interrupt map2 define MBOX0_A 0x348 Mailbox 0 define MBOX1_A 0x34C Mailbox 1 define MBOX2_A 0x350 Mailb...

Page 147: ...ge 5 base address reg define VSI5_BD_A 0xFAC VMEbus slave image 5 bound address reg define VSI5_TO_A 0xFB0 VMEbus slave image 5 translation offset define VSI6_CTL_A 0xFB8 VMEbus slave image 6 control...

Page 148: ...R W parity error response define PCI_CSR_VGAPS 0x00000020 R VGA palette snoop define PCI_CSR_MWI_EN 0x00000010 R mem write and invalidate enable define PCI_CSR_SC 0x00000008 R special cycles define PC...

Page 149: ...m AM code define LSI_CTL_SUPER 0x00001000 R W VMEbus supervisory AM code define LSI_CTL_VCT_S 0x00000000 R W VMEbus single cycles only define LSI_CTL_VCT_SB 0x00000100 R W VMEbus single cycles and blo...

Page 150: ...bus add reg MASK scyc_en special cycle swap compare enable reister 0x00000000 define SCYC_EN 0xFFFFFFFF R W spceial cycle swap compare en MASK scyc_cmp special cycle compare data register 0x00000000 d...

Page 151: ...0C00000 R W VMEbus max data width D64 define DCTL_VAS_16 0x00000000 R W VMEbus address space A16 define DCTL_VAS_24 0x00010000 R W VMEbus address space A24 define DCTL_VAS_32 0x00020000 R W VMEbus add...

Page 152: ...F8 0x00070000 R W min off between xfers 1024 us define DGCS_VOFF9 0x00080000 R W min off between xfers 2 us define DGCS_VOFFA 0x00090000 R W min off between xfers 4 us define DGCS_VOFFB 0x000A0000 R W...

Page 153: ...received define LINT_STAT_LM1 0x00200000 R W Location monitor 1 received define LINT_STAT_LM0 0x00100000 R W Location monitor 0 received define LINT_STAT_MBOX3 0x00080000 R W MAILBOX 3 received defin...

Page 154: ...RQ5_5 0x00500000 R W PCI int LINT 5 for VME IRQ5 define LINT_MAP0_VIRQ5_6 0x00600000 R W PCI int LINT 6 for VME IRQ5 define LINT_MAP0_VIRQ5_7 0x00700000 R W PCI int LINT 7 for VME IRQ5 define LINT_MAP...

Page 155: ...int LINT 0 for ACFAIL define LINT_MAP1_ACFAIL_1 0x10000000 R W PCI int LINT 1 for ACFAIL define LINT_MAP1_ACFAIL_2 0x20000000 R W PCI int LINT 2 for ACFAIL define LINT_MAP1_ACFAIL_3 0x30000000 R W PC...

Page 156: ...LINT_MAP1_LERR_3 0x00000030 R W PCI int LINT 3 for LERR define LINT_MAP1_LERR_4 0x00000040 R W PCI int LINT 4 for LERR define LINT_MAP1_LERR_5 0x00000050 R W PCI int LINT 5 for LERR define LINT_MAP1_...

Page 157: ..._MBOX3 0x00080000 R W VMEbus int MAILBOX 3 define VINT_STAT_MBOX2 0x00040000 R W VMEbus int MAILBOX 2 define VINT_STAT_MBOX1 0x00020000 R W VMEbus int MAILBOX 1 define VINT_STAT_MBOX0 0x00010000 R W V...

Page 158: ...ine VINT_MAP0_LINT4_3 0x00030000 R W VME int 3 for LINT4 define VINT_MAP0_LINT4_4 0x00040000 R W VME int 4 for LINT4 define VINT_MAP0_LINT4_5 0x00050000 R W VME int 5 for LINT4 define VINT_MAP0_LINT4_...

Page 159: ...for SW_IACK define VINT_MAP1_SW_IACK_6 0x00060000 R W VME int 6 for SW_IACK define VINT_MAP1_SW_IACK_7 0x00070000 R W VME int 7 for SW_IACK define VINT_MAP1_VERR_D 0x00000000 R W VME int disable for V...

Page 160: ...OC MON3 define LINT_MAP2_LM2_0 0x00000000 R W PCI int LINT 0 for LOC MON2 define LINT_MAP2_LM2_1 0x01000000 R W PCI int LINT 1 for LOC MON2 define LINT_MAP2_LM2_2 0x02000000 R W PCI int LINT 2 for LOC...

Page 161: ...INT_MAP2_MB1_2 0x00000020 R W PCI int LINT 2 for MAILBOX1 define LINT_MAP2_MB1_3 0x00000030 R W PCI int LINT 3 for MAILBOX1 define LINT_MAP2_MB1_4 0x00000040 R W PCI int LINT 4 for MAILBOX1 define LIN...

Page 162: ...for MAILBOX0 define VINT_MAP2_MB0_7 0x00000007 R W VME int VIRQ 7 for MAILBOX0 sema0 semaphore 0 register define SEMA0_SEM3 0x80000000 R W semaphore 3 define SEMA0_SEM2 0x00800000 R W semaphore 2 defi...

Page 163: ...L_VARB_P 0x04000000 R W VME arbitration Priority define MISC_CTL_VARBTO_1 0x00000000 R W VME arb time out disabled define MISC_CTL_VARBTO_2 0x01000000 R W VME arb time out 16 us define MISC_CTL_VARBTO...

Page 164: ...I O space define VSI_CTL_LAS_C 0x00000002 R W PCIbus configuration space vsi x _bs VMEbus slave image 0 base address register define VSI0_BS 0xFFFFF000 R W VME slave image 0 base add MASK define VSI1...

Page 165: ..._ctl VMEbus CSR control register define VCSR_CTL_EN 0x80000000 R image enable define VCSR_CTL_LAS_M 0x00000000 R W PCIbus memory space define VCSR_CTL_LAS_I 0x00000001 R W PCIbus I O space define VCSR...

Page 166: ...TE_CONFIG_BYTE 0x0B define WRITE_CONFIG_WORD 0x0C define WRITE_CONFIG_DWORD 0x0D PCI Return codes define SUCCESSFUL 0x00 define NOT_SUCCESSFUL 0x01 PCI Config Space Regs define PCI_CS_VENDOR_ID define...

Page 167: ...iguration_area unsigned char function unsigned char bus_number unsigned char device_and_function unsigned char register_number unsigned long data int write_configuration_area unsigned char function un...

Page 168: ...er define SMBSLVEVT 0x0A SMBus slave event register define SMBSLVDAT 0x0B SMBus slave data register SMBus host status register bit defines define HSTSTSFAIL 0x10 Failed bus transaction define HSTSTSCO...

Page 169: ...ong pat 4 0x55555555 0xCCCCCCCC 0x66666666 0xFFFFFFFF void main void unsigned long i x unsigned char bdat unsigned char brd unsigned int wdat unsigned int wrd unsigned long ldat unsigned long lrd prin...

Page 170: ...i 0x18 i 0x8000 i 2 w_ptr wdat wdat wdat w_ptr unsigned int far buf_ptr wdat unsigned int pat x for i 0x18 i 0x8000 i 2 wrd w_ptr if wdat wrd printf FAILED nWORD DATA ADDR Fp WR 4X RD 4X n w_ptr wdat...

Page 171: ...and test buf with DATA ADD LONG for x 0 x 4 x l_ptr unsigned long far MK_FP 0xD800 0x18 for i 0x18 i 0x8000 i 4 l_ptr i l_ptr unsigned long far MK_FP 0xD800 0x18 for i 0x18 i 0x8000 i 4 lrd l_ptr if l...

Page 172: ...General Purpose Output 28 tmr 2 define GPO_T3 0x08 PIX General Purpose Output 27 tmr 3 define GPO_CLR 0xA7 PIX General Purpose Output CLR TMRS define TIMER_CNTR1 0x00 Timer counter 1 offset define TI...

Page 173: ...ers F define CW_RB_CNT 0x00 W Read back count define CW_RB_STAT 0x00 W Read back status define CW_RB_C0 0x02 W Read back counter 0 define CW_RB_C1 0x04 W Read back counter 1 define CW_RB_C2 0x08 W Rea...

Page 174: ...define WRITE_CONFIG_DWORD 0x0D PCI Return codes define SUCCESSFUL 0x00 define NOT_SUCCESSFUL 0x01 PCI Config Space Regs define PCI_CS_VENDOR_ID define PCI_CS_DEVICE_ID define PCI_CS_COMMAND define PC...

Page 175: ...signed char bus_number unsigned char device_and_function unsigned char register_number unsigned long data int write_configuration_area unsigned char function unsigned char bus_number unsigned char dev...

Page 176: ...d char bus_number unsigned char device_and_function int ret_status unsigned short ax bx flags _CX device_id _DX vendor_id _SI index _AH PCI_FUNCTION_ID _AL FIND_PCI_DEVICE geninterrupt 0x1a ax _AX bx...

Page 177: ..._BL device_and_function _DI register_number _AH PCI_FUNCTION_ID _AL function geninterrupt 0x1a ecx _ECX ax _AX flags _FLAGS if flags CARRY_FLAG 0 ret_status HIGH_BYTE ax if ret_status SUCCESSFUL data...

Page 178: ...N_ID _AL function geninterrupt 0x1a ax _AX flags _FLAGS if flags CARRY_FLAG 0 ret_status HIGH_BYTE ax else ret_status NOT_SUCCESSFUL return ret_status void outpd unsigned short port unsigned long valu...

Page 179: ...unsigned char global variables unsigned char bus dev_func the following globals are used in other files as extern variables unsigned char tmr_status t1_stat t2_stat t3_stat unsigned int tmr_cnt t1_cn...

Page 180: ...rpose input bits 8 15 gpo_base pwr_mgm_base 0x37 PIX general purpose output bits 24 31 disable disable timers by reloading the control word outp timer_base TIMER_CNTL CW_SC0 CW_LSBMSB CW_M2 outp timer...

Page 181: ...CW_SC2 CW_LSBMSB CW_M2 tmr_status 0 test_int 100 load_counter 2 0xFFFF do if t2_count t2 break test_int delay 1 while test_int disable timers by reloading the control word outp timer_base TIMER_CNTL C...

Page 182: ..._base gpo_org GPO_T1 GPO_T2 GPO_T3 if t1 t2 t3 printf PASSED n else printf FAILED n if t1 printf TIMER 1 failed n if t2 printf TIMER 2 failed n if t3 printf TIMER 3 failed n do_exit 2 do orderly exit...

Page 183: ...unsigned long t2_count timer 2 count extern unsigned long t3_count timer 3 count extern unsigned char tmr_status extern unsigned int gpi_base extern unsigned int gpo_base extern unsigned int timer_bas...

Page 184: ...GPO_T3 enable init_timer_int restore_orig_int purpose Using the interrupt assigned the original vector is restored and the programmable interrupt controller is disabled Prerequisite The interrupt line...

Page 185: ..._M2 outp timer_base TIMER_CNTR2 unsigned char lsb outp timer_base TIMER_CNTR2 unsigned char msb break case 3 select counter 3 LSB then MSB mode 2 outp timer_base TIMER_CNTL CW_SC2 CW_LSBMSB CW_M2 outp...

Page 186: ...RB_CNT CW_RB_STAT CW_RB_C1 status inp timer_base TIMER_CNTR2 0xFF lsb inp timer_base TIMER_CNTR2 0xFF msb inp timer_base TIMER_CNTR2 0xFF msb msb 8 count lsb msb break case 3 select counter 3 LSB then...

Page 187: ...rg GPO_T1 clear timer 1 status bit if tmr_status GPI_T2 t2_count outp gpo_base gpo_org GPO_T2 clear timer 2 status bit if tmr_status GPI_T3 t3_count outp gpo_base gpo_org GPO_T3 clear timer 3 status b...

Page 188: ...06 01 07 0 0 0 0 0 define CLK_DAYAL 0x07 01 07 M 0 0 0 0 define CLK_DATE 0x08 01 31 0 0 define CLK_MONTH 0x09 01 12 0 define CLK_YRS 0x0A 00 99 define WD_CMD 0x0B command register define WD_MSEC 0x0C...

Page 189: ...WatchDog Alarm Mask 1 deactivated and update with 0 time wd_ptr WD_CMD WD_TE WD_WAM wd_ptr WD_MSEC 0 load with 0 to disable wd_ptr WD_SEC 0 load with 0 to disable wd_ptr WD_CMD WD_TE WD_WAM allow upda...

Page 190: ...190 F VMICPCI 7715 Product Manual...

Page 191: ...Floppy Drive B 91 floppy mapping 114 G graphics video resolutions 48 I I O address space 39 114 features 24 port map 39 installation 34 Intels 21143 49 internal timer counter 60 interrupt line assign...

Page 192: ...r locations 31 Return Material Authorization RMA number 71 S screen resolutions 48 Select Timer 65 Serial I O COM1 2 3 4 41 serial port mapping 114 serial ports 47 Setting the time 90 SMC Super I O ch...

Search results

Summary of Contents for VMICPCI-7715

Reviews:

VMIC VMICPCI-7715, Product Manual, Page: 1 / 192

Search results

Summary of Contents for VMICPCI-7715

Reviews: