Vmetro M5210RP-EFF, User Manual, Page: 80 / 130

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M5000 Series: User Guide Issued June 20, 2007
Miscellaneous Functions
7.3 Interrupt Routing
In order to support a flexible interrupt routing mechanism, all interrupt source and destination
signals are routed to a PLD which provides the actual routing between sources and destinations:
FIGURE 7-1
Interrupt
Routing
The following devices are considered as possible interrupt sources:
•
2 PPMC sites (4 interrupt lines A,B,C and D)
•
Mezzanine PMC sites (4 interrupt lines A,B,C and D)
•
TUNDRA Universe IID VME-to-PCI bridge (2 interrupt lines i0 and i1)
•
Intel LXT9785 Fast Ethernet controller (1 interrupt line E0)
•
AMCC 440GX PowerPC processor (1 interrupt line X)
•
3 PCI6540 PCIX-to-PCIX bridges (2 interrupt lines P and S)
•
ISP2312 PCIX-to-Dual FC Host Adapter (2 interrupt lines A and B)
•
MERCURY PXB++ PCI-to-Race++ Bridge (4 interrupt lines A,B,C and D)
The following devices are considered as possible interrupt destinations:
•
PPMC#1 site (4 interrupt lines A,B,C and D)
•
AMCC 440GX PowerPC processor (16 interrupt lines P0 to P15)
•
Universe PCI-to-VME bridge
The following routing tables show the current interrupt mapping:
Interrupt Routing
CPLD
PowerPC
Processor
P0..P15 X
PowerPC
Processor
P0..P15 X
Dual FC
Host Adapter
A,B
Dual FC
Host Adapter
A,B
PCI-to-VME
Bridge
i2..i7
i0,i1 PCI-to-VME
Bridge
i2..i7
i0,i1
PCI-to-RACE++
Bridge
A,B,
C,D
PCI-to-RACE++
Bridge
A,B,
C,D
PCIX-to-PCIX
Bridge
P,S
PCIX-to-PCIX
Bridge
P,S
PMC
A,B,
C,D
PMC
A,B,
C,D
Ethernet
E0
Ethernet
E0
MEZZ
A,B,
C,D
MEZZ
A,B,
C,D
PMC
A,B,
C,D
PMC
A,B,
C,D