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VT82885

Real Time Clock

VIA Technologies, Inc.

FEATURES

Drop-in replacement for IBM AT computer
clock/calendar.

Pin configuration closely matches  the
DS12887, DS12885and DS12885Q

Counts seconds, minutes, hours, days,
day of the week, date, month, and year
with leap year compensation

Binary or BCD representation of time,
calendar and alarm

12- or 24-hour clock with AM and PM in
12-hour mode

Daylight Savings Time option

Intel bus timing

Multiplex bus for pin efficiency

Interfaced with software as 128 RAM
locations

- 14 bytes of clock and control registers
- 114 bytes of general purpose RAM

Programmable square wave output signal

Bus-compatible interrupt signals (IRQ#)

Three interrpts are separately software-
maskable and testable

- Times-of-day alarm once/second to 

once/day

- Periodic rates from 122 

µ

s to 500 ms

- End of clock update cycle

Optional 28-pin PLCC surface mount
package

DESCRIPTION

The VT82885 Real Time Clock is designed
to be a direct replacement for the DS12885.
The VT82885 is identical in form, fit and
function to the DS12885. It has 114 bytes of
general purpose RAM. Access to this RAM
space is determined by the logic level
presented on AD6 during the address
portion of an access cycle. An external
crystal and battery are the only components
required to maintain time-of-day and
memory status in the absence of power. A
complete description of operating conditions,

electrical characteristics, bus timing and pin
descriptions follows.

PIN ASSIGNMENT

1

2

GND

3

4

5

X1

X2

AD0

AD1

24

V

CC

23

22

21

20

19

18

17

SQW

NC

RCLR#

V

BAT

IRQ#

RESET#

RD#

6

7

8

AD2

AD3

AD4

AD5

AD6

AD7

GND

9

10

11

12

16

15

14

13

NC

WR#

AS

CS#

VT82885 24 PIN DIP

AD0

AD1

AD2

AD3

AD4

AD5

NC

RCLR#

V

BAT

IRQ#

RESET#

RD#

GND

WR#

X
2

X
1

G
N
D

N
C

V

CC

S
Q
W

N
C

A
D
6

N
C

A
D
7

G
N
D

C
S
#

A
S

N
C

1

2

7

6

3

9

8

10

13 14 15 16 17

20

21

22

23

24

27

28

25

11

19

18

4

26

5

VT82885 28-PIN PLCC

PIN DESCRIPTION

AD0-AD7

- Multiplexed Address/Data Bus

NC

- No Connection

CS#

- Chip Select

AS

- Address Strobe

Summary of Contents for VT82885

Page 1: ...SCRIPTION The VT82885 Real Time Clock is designed to be a direct replacement for the DS12885 The VT82885 is identical in form fit and function to the DS12885 It has 114 bytes of general purpose RAM Access to this RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle An external crystal and battery are the only components required to maintain time...

Page 2: ...ion will continue to operate and all of the RAM time calen dar and alarm memory locations remain nonvolatile regardless of the level of the VCC input When VCC is applied to the VT82885 and reaches a level of greater than 4 25 volts the device becomes ac cessible after 100 ms provided that the oscillator is running and the oscillator countdown chain is not in reset see Register A This time period a...

Page 3: ...ut on the VCC pin VBAT Battery input for any standard 3 volt lithium cell or energy source Battery vol tage must be held between 2 5 and 3 4 volts for proper operation A maximum load of 5 µA at 25 C in the absence of VCC power should be used to size the external energy source SQW Square Wave Output The SQW pin can output a signal from one of 13 taps provided by the internal divider stages of the R...

Page 4: ...ithin the VT82885 RD Read Strobe The RD pin identifies the time period when the VT82885 drives the bus with read data The RD signal is the same definition as the Output Enable OE signal on a typical memory WR Write Strobe The WR pin is used to indicate a write cycle CS Chip Select Input The Chip Select signal must be asserted low for a bus cycle in the VT82885 to be accessed CS must be kept in the...

Page 5: ... read except the following 1 Registers C and D are read only 2 Bit 7 of Register A is read only 3 The high order bit of the seconds byte is read only The contents of four registers A B C and D are described in the Register section FIGURE 2 ADDRESS MAP VT82885 TIME CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes The time calendar an...

Page 6: ...r data is low Sev eral methods of avoiding any possible incor rect time and calendar reads are covered later in this text The three alarm bytes can be used in two ways First when the alarm time is written in the appropriate hours minutes and seconds alarm locations the alarm interrupt is initi ated at the specified time each day if the alarm enable bit is high The second use condition is to insert...

Page 7: ...which are set remain stable throughout the read cycle All bits which are set high are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed One two or three bits can be set when reading Register C Each utilized flag bit should be examined when read to ensure that no interrupts are lost The second flag bit usage method is with fully...

Page 8: ...al time clock that avoid any possibility of accessing inconsistent time and calendar data The first method uses the update ended interrupt If enabled an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date information If this interrupt is used the IRQF bit in Regis ter C should be cleared before leaving the interrupt routine A second ...

Page 9: ...IE SQWE DM 24 12 DSE SET When the SET bit is a zero the update transfer functions normally by advancing the counts once per second When the SET bit is written to a one any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing SET is a read write bit that is not modified by RE SET or internal functions of the...

Page 10: ...ts are cleared after Register C is read by the program or when the RESET pin is low PF The Periodic Interrupt Flag PF is a read only bit whcih is set to a one when an edge is detected on the selected tap of the divider chain The RS3 through RS0 bits establish the periodic rate PF is set to a one independent of the state of the PIE bit When both PF and PIE are ones the IRQ signal is active and will...

Page 11: ...TER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 4 5 5 0 5 5 V 1 Input Logic 1 VIH 2 2 VCC 0 3 V 1 Input Logic 0 VIL 0 3 0 8 V 1 DC ELECTRICAL CHARACTERISTICS 0 C TO 70 C VCC 4 5 TO 5 5V PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Current ICC1 5 10 mA 2 Input Leakage IIL 1 0 1 0 µA 3 I O Leakage ILO 1 0 1 0 µA 4 Input Current IMOT 1 0 500 µA 3 Output 2 4V IOH 1 0 mA 1 5 Output...

Page 12: ...Rise tASD 25 ns Pulse Width AS ALE High PWASH 60 ns Delay Time AS alE to DS E Rise tASED 40 ns Output Data Delay Time from DS E or RD tDDR 20 120 ns DataSetup Time tDSW 100 ns Reset Pulse Width tRWL 5 µs IRQ Release from DS tIRDS 2 µs IRQ Release from RESET tIRR 2 µs Delay Time before Update Cycle tBUC 244 µs Periodic Interrupt Time Interval tPI See Table 1 Time of Update Cycle tUC 1708 µs NOTES 1...

Page 13: ...13 VT82885 Real Time Clock VIA Technologies Inc D U T 5 VOLTS 1 1 KΩ 50 pF 680Ω VT82885 BUS TIMING FOR WRITE CYCLE ...

Page 14: ...14 VT82885 Real Time Clock VIA Technologies Inc AS RD WR CS AD0 AD7 PWEL tASD tASD PWASH tCYC tCS tASED PWEH tDSW tAHL tASL tCH tDHW VT82885 BUS TIMING FOR READ CYCLE ...

Page 15: ...5 Real Time Clock VIA Technologies Inc AS RD WR CS AD0 AD7 PWEL tASD tASD PWASH tCYC tCS tASED PWEH tDDR tAHL tASL tDHR tCH VT82885 IRQ RELEASE DELAY TIMING RD RESET IRQ tRDS tIRR tRWL POWER DOWN POWER UP TIMING ...

Page 16: ...CC slew from 4 5V to 0V CS at VIH tF 300 µs VCC slew from 0V to 4 5V CS at VIH tR 100 µs CS at VIH after Power Up tREC 20 200 ms tA 25 C PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention tDR 10 years NOTE The real time clock will keep time to an accuracy of 1 minute per month during data retention time for the period of tDR WARNING Under no circumstances are negative undershots of a...

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