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External Trigger Enable Register

VCM-DAS-3 Reference Manual

24

External Trigger Enable Register

EXTRIG (Read/Write) 0303h

7

6

5

4

3

2

1

0

–

–

–

–

–

–

–

TRIGEN

Table 14: EXTRIG Bit Assignments

Bit

Mnemonic

Description

7-1

–

Unused. These bits have no function.

0

TRIGEN

Trigger Enable

– When the external trigger is enabled, digital I/O line C0 will

update all DACs simultaneously when it is brought low. This can be done either
by an external signal, when C0 is in input mode, or in software, when C0 is in
output mode. If using an external trigger, make sure that the lower half of Port C
is in input mode.

1 = Enable
0 = Disable

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Summary of Contents for VCM-DAS-3

Page 1: ...Reference Manual REV February 2020 VCM DAS 3 Analog Output Digital I O Module for the PC 104 Bus ...

Page 2: ...s document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are trademarks o...

Page 3: ...e vcmdas3support asp contains additional information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and manufacturers links for chips used in this product BIOS information and upgrades Utility routines and benchmark software Note This is a private page for VCM DAS 3 users that can be accessed only be entering this ...

Page 4: ...tion 11 Hardware Assembly 11 Stack Arrangement Example 11 Configuration 12 Jumper Blocks 12 Jumpers As Shipped Configuration 12 Jumper Summary 13 Base Address Configuration 14 Bit Mode Configuration 15 Enhanced Mode Configuration 16 Power up Span Range Configuration 16 Registers 17 I O Port Mapping 17 I O Port Register Functions 18 Enhanced Mode Registers 19 Enhanced Control Register 19 Enhanced M...

Page 5: ...ng 28 Offset Binary Coding 29 Analog Output Programming 31 External Trigger Update 31 Load DAC Operation 31 Analog Output Code Example 32 Calibration 34 Setting the Gain 34 Reading the Gain 34 Enhanced Mode Operations 35 Reading DAC Data 35 Reading the Span of a Channel 35 Setting a Channel to Sleep Mode 36 Reading the Sleep Status of a Channel 36 Digital I O 37 Signal Direction 37 Signal Polarity...

Page 6: ...ad back of DAC and SPAN codes Reset power up to 0V outputs for all ranges External trigger 5V operation 24 channel digital I O The VCM DAS 3 module provides 16 single ended analog outputs and 24 digital I O channels Fully compatible at the register and connector level with the Diamond Systems Ruby MM DAC board VCM DAS 3 also provides enhanced mode operation that extends its capabilities In enhance...

Page 7: ...for all channels Gain Temp Coefficient 2 ppm C Update Method Simultaneous individual or external trigger Reset Outputs reset to 0V when board is jumpered for Enhanced Mode mid scale otherwise Digital I O Channels 24 Compatibility CMOS TTL 82C55 Mode 0 only Low Input Voltage 0 3V min 0 8V max High Input Voltage 2 0V min 5 5V max Low Output Voltage 0 4V max High Output Voltage 3 0V min Output Curren...

Page 8: ...opean Union EU beginning July 1 2006 VersaLogic Corporation is committed to supporting customers with high quality products and services meeting the European Union s RoHS directive Warnings ELECTROSTATIC DISCHARGE Warning Electrostatic discharge ESD can damage circuit boards disk drives and other components The circuit board must only be handled at an ESD workstation If an approved station is not ...

Page 9: ...ation Your name the name of your company and your phone number The name of a technician or engineer that can be contacted if any questions arise Quantity of items being returned The model and serial number barcode of each item A detailed description of the problem Steps you have taken to resolve or recreate the problem The return shipping address Warranty Repair All parts and labor charges are cov...

Page 10: ...e VCM DAS 3 complies with all PC 104 standards Dimensions are given below to help with pre production planning and layout Figure 1 Dimensions and Mounting Holes Not to scale All dimensions in inches 2 2 3 375 0 00 0 15 3 05 0 1875 0 00 3 15 3 3625 3 575 0 20 Pin 1 ...

Page 11: ...PROFILE Figure 2 Side Profile Not to scale All dimensions in inches External Connectors CONNECTOR LOCATIONS Figure 3 Connector Locations Top Not to scale J2 J1 J3 J4 Pin 1 J5 B1 A1 C0 D0 C19 D19 49 50 1 2 B32 A32 1 1 2 2 9 39 10 40 V1 V2 V3 0 44 0 44 0 06 ...

Page 12: ...unctions and Interface Cables Connector Function Mating Connector Transition Cable Cable Description Page J1 Digital I O A0 A7 FCI 89361 710LF 2mm 10 pin IDC 8 J2 Analog Outputs Digital I O B0 C7 FCI 89361 740LF CBR 4004A 12 2mm 40 pin to 40 pin IDC to screw terminal board CBR 4004B 9 J3 Analog Outputs Digital I O Standard 0 1 50 pin cable mount IDC Diamond Systems C 50 18 Data acquisition 50 cond...

Page 13: ...7 The pinout of the connector is shown in Table 2 Table 2 J1 I O Connector Pinout J1 Pin Signal Name Function 1 Ground Ground 2 DIO A7 Digital I O A7 3 DIO A6 Digital I O A6 4 DIO A5 Digital I O A5 5 DIO A4 Digital I O A4 6 DIO A3 Digital I O A3 7 DIO A2 Digital I O A2 8 DIO A1 Digital I O A1 9 DIO A0 Digital I O A0 10 Ground Ground ...

Page 14: ...tput 3 IO11 14 VOUT 11 Analog Out Ch 11 2 IO12 15 Ground Ground 1 GND2 16 VOUT 12 Analog Out Ch 12 J4 5 IO13 17 VOUT 13 Analog Out Ch 13 Analog 4 IO14 18 VOUT 14 Analog Out Ch 14 Output 3 IO15 19 VOUT 15 Analog Out Ch 15 2 IO16 20 Ground Ground 1 GND2 21 DIO B7 Digital I O B7 J6 5 IO17 22 DIO B6 Digital I O B6 Digital I O B 4 IO18 23 DIO B5 Digital I O B5 3 IO19 24 DIO B4 Digital I O B4 2 IO20 25 ...

Page 15: ...T 03 Analog Output 3 33 DIO B7 Digital I O B7 9 Ground Ground 34 DIO B6 Digital I O B6 10 VOUT 04 Analog Output 4 35 DIO B5 Digital I O B5 11 Ground Ground 36 DIO B4 Digital I OB4 12 VOUT 05 Analog Output 5 37 DIO B3 Digital I O B3 13 Ground Ground 38 DIO B2 Digital I O B2 14 VOUT 06 Analog Output 6 39 DIO B1 Digital I O B1 15 Ground Ground 40 DIO B0 Digital I O B0 16 VOUT 07 Analog Output 7 41 DI...

Page 16: ...t on a table top or be secured to a base plate When bolting the unit down make sure to secure all four standoffs to the mounting surface to prevent circuit board flexing Standoffs are secured to the top circuit board using four pan head screws Standoffs and screws are available as part number VL HDW 101 An extractor tool is available part number VL HDW 201 to separate the PC 104 modules from the s...

Page 17: ...M DAS 3 Reference Manual 12 Configuration Jumper Blocks JUMPERS AS SHIPPED CONFIGURATION Figure 6 Jumper Block Locations 3 3 V1 V2 V3 1 3 5 7 9 11 13 15 1 3 5 7 1 3 5 7 2 4 6 8 2 4 6 8 2 4 6 8 10 12 14 16 ...

Page 18: ... MM board In 16 V1 11 12 to 1 2 Base Address Selector A base address of 0x000 to 0x3F0 can be selected The last digit is always 0 First Digit 11 12 9 10 0 In Out 1 Out In 2 Out In 3 Out Out Second Digit 7 8 5 6 3 4 1 2 0 In In In In 1 In In In Out 2 In In Out In 3 In In Out Out 4 In Out In In 5 In Out In Out 6 In Out Out In 7 In Out Out Out 8 Out In In In 9 Out In In Out A Out In Out In B Out In O...

Page 19: ...to 5V 27 Base Address Configuration As shipped the VCM DAS 3 is configured for a base address of 0x300 The card occupies up to 16 consecutive I O addresses in enhanced mode only eight I O addresses in compatible mode Jumper block V1 11 12 through V1 1 2 is used set the base address The base address can be configured from 0x000 to 0x3F0 on any 10h address boundary Figure 7 shows how to set the addr...

Page 20: ...e 8 bit ISA transactions Jumper V1 15 16 selects the bit mode When a jumper is present the board will operate on either 16 bit or 8 bit ISA bus When the jumper is removed the board is forced to perform only 8 bit ISA transactions The default setting is jumper installed 9 10 11 12 0 5 2 6 0 2 1 3 C E D F 4 A 9 B 1 7 3 8 1 2 3 4 5 6 7 8 The lower digit is always 0 Upper Digit Middle Digit Lower Digi...

Page 21: ...wo banks of eight registers and are not software programmable Enhanced mode provides three additional registers for more specific control of DAC operations The ENH_CON register enables you to set spans for specific DAC channels read DAC data and spans set DAC channels to sleep mode for power savings and set and read the gain for all channels Power up Span Range Configuration Jumper block V2 sets t...

Page 22: ...R Base Address F 0x30F Base Address E 0x30E Base Address D 0x30D Base Address C 0x30C Base Address B 0x30B ENCTRL ENCTRL Base Address A 0x30A ENDATHI ENDATHI Base Address 9 0x309 ENDATLO ENDATLO Base Address 8 0x308 DIOCTRL DIOCTRL Base Address 7 0x307 DIOC DIOC Base Address 6 0x306 DIOB DIOB Base Address 5 0x305 DIOA DIOA Base Address 4 0x304 EXTRIG EXTRIG Base Address 3 0x303 DACSEL Base Address...

Page 23: ...escription Page ENCTRL Enhanced control 19 ENDATHI Enhanced Data MSB 20 ENDATLO Enhanced Data LSB 20 DIOCTRL Digital I O control register 21 DIOC Digital I O port C data 23 DIOB Digital I O port B data 23 DIOA Digital I O port A data 23 EXTRIG External trigger enable 24 DACSEL DAC channel register 25 DACHI Analog output most significant data byte MSB 26 DACLO Analog output least significant data b...

Page 24: ...3 CTRL2 CTRL1 CTRL0 Function 0 0 0 0 Set Span 0V to 5V 0 0 0 1 Set Span 0V to 10V 0 0 1 0 Set Span 5V to 5V 0 0 1 1 Set Span 10V to 10V 0 1 0 0 Set Span 2 5V to 2 5V 0 1 0 1 Set Span 2 5V to 7 5V 0 1 1 0 Reserved Do not use 0 1 1 1 Reserved Do not use 1 0 0 0 Read DAC 1 0 0 1 Read Span 1 0 1 0 Load DAC LDAC 1 0 1 1 DAC Sleep 1 1 0 0 Reserved Do not use 1 1 0 1 Reserved Do not use 1 1 1 0 Set Gain ...

Page 25: ...speed which limits the usefulness of his bit for anything other than factory debugging of the design ENHANCED MODE DATA REGISTERS ENDATHI MSB Read 0309h 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 ENDATLO LSB Read Write 0308h 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 The data format of these registers depends on the operation executed in the ENCTRL register See the sections listed below for inform...

Page 26: ...Port A Direction These bits control the direction of DIO port A A7 A0 0 Output 1 Input 3 DIRCHI DIO Port C MSB Direction These bits control the direction of the upper half of DIO port C C7 C4 0 Output 1 Input 2 Unused This bit has no function 1 DIRB DIO Port B Direction These bits control the direction of DIO port B B7 B0 0 Output 1 Input 0 DIRCLO DIO Port C LSB Direction These bits control the di...

Page 27: ... C0 Digital Input Data Data read from these registers returns the current input state of the digital port signals on connectors J1 and J2 Data is not inverted When a signal line is high the bit reads as 1 when a signal line is low the bit reads as 0 To operate a port in input mode you must first set the direction of the port to input by setting the appropriate bit in the DIOCTRL register If a port...

Page 28: ...O A5 DIO A4 DIO A3 DIO A2 DIO A1 DIO A0 Table 13 Digital Output Data Bit Assignments Bit Mnemonic Description D7 D0 DIO A7 A0 DIO B7 B0 DIO C7 C0 Digital Output Data Data written to these registers is driven onto the digital port signals on connectors J1 and J2 Data is not inverted When a bit is set to 1 the signal line is driven high when a bit is reset to 0 the signal line is driven low To opera...

Page 29: ...on 7 1 Unused These bits have no function 0 TRIGEN Trigger Enable When the external trigger is enabled digital I O line C0 will update all DACs simultaneously when it is brought low This can be done either by an external signal when C0 is in input mode or in software when C0 is in output mode If using an external trigger make sure that the lower half of Port C is in input mode 1 Enable 0 Disable ...

Page 30: ...Assignments Bit Mnemonic Description 7 4 Unused These bits have no function 3 0 SEL Channel Selection These bits select the DAC channel upon which digital output functions will be performed SEL3 SEL2 SEL1 SEL0 Selected Channel 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 ...

Page 31: ...the DACLO register to form the 12 bit analog output value Table 17 DACLO Bit Assignments Bit Mnemonic Description 7 0 DACLO Analog Output DATA LSB Digital to analog data bits DA7 DA0 DA0 is the least significant bit This register is used with the DACHI register to form the 12 bit analog output value DAC READ REGISTERS DACALL1 Read 0301h 7 6 5 4 3 2 1 0 DA11 DA10 DA9 DA8 DACALL0 Read 0300h 7 6 5 4 ...

Page 32: ...ull scale refers to the output voltage for a code of 0 and positive full scale refers to the output voltage for a code of 4095 Table 18 Analog Output Ranges and Resolution Full Scale Voltage Bipolar or Unipolar Range Name Negative Full Scale Positive Full Scale Resolution 1 LSB 10V Bipolar 10V 10V 9 9951V 4 88mV 5V Bipolar 5V 5V 4 9963V 2 44mV 2 5V Bipolar 2 5V 2 5V 2 4988V 1 22mV 7 5V Bipolar 2 5...

Page 33: ...ht binary digital values are given by Where Analog Applied voltage Digital A D conversion data Step 0 00244140625 for 0 10V range 0 00122070313 for 0 5V range 0 0006103515625 for 0 2 5V range Table 19 Straight Binary Data Format 0 2 5V Range 0 5V Range 0 10V Range Hex Decimal Comment 2 5000 5 0000 10 0000 Out of range 2 4993 4 9987 9 9975 FFFh 4095 Maximum positive voltage 1 2500 2 5000 5 0000 800...

Page 34: ...t Binary Data Format Symmetrical Ranges 2 5V Output Voltage 5V Output Voltage 10V Output Voltage Hex Decimal Comment 2 5000 5 0000 10 0000 Out of range 2 4987 4 9975 9 9951 FFFh 4095 Maximum positive voltage 1 2500 2 5000 5 0000 C00h 3072 Positive half scale 0 6250 1 2500 2 5000 A00h 2560 Positive quarter scale 0 00122 0 00244 0 00488 801h 2049 Positive 1 LSB 0 0000 0 0000 0 0000 800h 2048 Zero gr...

Page 35: ...ment 7 5000 Out of range 7 4975 FFFh 4095 Maximum positive voltage 3 7500 A00h 2560 Positive half scale 1 8750 700h 1792 Positive quarter scale 0 00244 401h 1025 Positive 1 LSB 0 0000 400h 1024 Zero ground voltage 0 00244 3FFh 1023 Negative 1 LSB 0 6250 300h 768 Negative quarter scale 1 2500 200h 512 Negative half scale 2 5000 000h 0 Maximum negative voltage ...

Page 36: ...CLO register EXTERNAL TRIGGER UPDATE An external trigger is enabled by setting the TRIGEN bit in the EXTRIG register at I O port 0x303 When the external trigger is enabled digital I O line C0 will update all DACs simultaneously when it is brought low This can be done either by an external signal when C0 is in input mode or in software when C0 is in output mode If using an external trigger make sur...

Page 37: ...within range Returns 0 if no errors 1 if timeout occurs Examples Output 5 000V on channel 0 x LIB_das3aout 0 1 5 000 Output 7 500V on channel 1 x LIB_das3aou 1 3 7 500 Enhanced Control Register BASE 0xA D7 D6 D5 D5 D3 D2 D1 D0 EC3 EC2 EC1 EC0 DAC CHANNEL 0V to 5V 0 0 0 0 0V to 10V 0 0 0 1 5V to 5V 0 0 1 0 10V to 10V 0 0 1 1 2 5V to 2 5V 0 1 0 0 2 5V to 7 5V 0 1 0 1 DIM value AS INTEGER DIM hidac A...

Page 38: ...ge fullscale 4096 END IF Limit excursion IF value 4095 THEN value 4095 END IF Separate low byte from high nibble lodac value AND HFF hidac value AND HF00 256 Set selected DAC channel to the desired range ENHANCED MODE REGISTER OUT BASE HA range 16 channel Set selected DAC channel to desired voltage OUT BASE lodac OUT BASE 2 channel OUT BASE 1 hidac A single read updates all outputs x INP BASE Wait...

Page 39: ...then write the gain value to the ENDATLO register at I O port 0x308 The following procedure is recommended for setting the gain 1 Select channel 0 by writing 0h to the DACSEL register at I O port 0x302 2 Output the code for 0V by writing 0h to both the DACHI and DACLO registers 3 Using high precision volt meter VOM read the voltage on channel 0 The voltage read is the offset 4 Output the code for ...

Page 40: ...30A combined with the channel number in the SEL field of the same register 2 Read the ENDATHI register and then the ENDATLO register The 12 bits of the output voltage code are offset toward the MSB as shown below ENDATHI MSB Read 0309h 7 6 5 4 3 2 1 0 D11 D10 D9 D8 D7 D6 D5 D4 ENDATLO LSB Read 0308h 7 6 5 4 3 2 1 0 D3 D2 D1 D0 0 0 0 0 READING THE SPAN OF A CHANNEL To read the span of a channel 1 P...

Page 41: ...l remains in sleep mode until a voltage output code is written to it READING THE SLEEP STATUS OF A CHANNEL To read the sleep status of a channel 1 Perform a Read Span operation by writing 9h to the CTRL field of the ENCTRL register at I O port 0x30A combined with the channel number in the SEL field of the same register 2 Read the SLEEPSTAT bit bit 4 of the ENDATLO register at I O port 0x308 as sho...

Page 42: ... low logic level is represented by a 0 Since Opto 22 modules invert the logic sense of signals passed through them the register to module interface is negative logic The resulting data interface levels between the VCM DAS 3 and I O rack modules are shown below Data Written I O Pin Output Modules Input Modules I O Pin Data Read 0 Low Power On Voltage Present Low 0 1 High Power Off Voltage Absent Hi...

Page 43: ...chnology LTC2704 PC 104 Specification PC 104 Consortium PC 104 Resource Guide PC 104 Plus Specification VersaLogic Corporation PC 104 Resource Guide General PC Documentation Microsoft Press The Programmer s PC Sourcebook General PC Documentation Powell s Books The Undocumented PC A A ...

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