Multi-purpose I/O
41
VL-EPU-4012 Hardware Reference Manual
The table below lists the pinout of the SPX connector.
Table 10: SPX Connector Pinout
Pin
Signal
Function
1
V5_SPX
+5.0 V
2
CLK
SPX Clock
3
GND
Ground
4
MISO
Master input, Slave output
5
GND
Ground
6
MOSI
Master output, Slave input
7
GND
Ground
8
SS0#
Chip Select 0
9
SS1#
Chip Select 1
SPI is, in its simplest form, a three wire serial bus. One signal is a clock, driven only by the
permanent master device on-board. The others are Data In and Data Out with respect to the
master. The SPX implementation on the Owl supports chip selects. The master device initiates
all SPI transactions. A slave device responds when its chip select is asserted and it receives clock
pulses from the master. All four common SPI modes are supported with clock polarity and clock
idle state controls.
The SPI clock is derived from a 33 MHz PCI clock and can be software-configured to operate at
the following frequencies:
8.25 MHz (33 MHz/4)
4.125 MHz (33 MHz/8)
2.0625 MHz (33 MHz/16)
1.03125 MHz (33 MHz/32)
Cabling
An adapter cable, part number CBR-0901, is available. This is a 9-inch, 9-pin Pico-Clasp to Dual
SPX cable.
If your application requires a custom cable, the following information will be useful:
EPU-4012 Board Connector
Mating Connector
Molex 501568-0907
Molex 501330-0900
