Connecting the Video Display
12
– Reference
EPM-VID-3 Reference Manual
LVDS
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
The integrated LVDS Flat Panel Display in the EPM-VID-3 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus 3 bits of
timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 85 MHz. Adapter cable VL-CBL-2010 or VL-CBL-2011 can
be used to connect J4 to the flat panel display connector.
The 3.3 V power provided to pins 19 and 20 of J4 is protected by a 1 Amp fuse.
See the
Connector Location Diagram
on page 7 for connector location information.
Table 4: LVDS Flat Panel Display Pinout
J4
Pin
Signal
Name
Function
Hirose or JAE
Connector
1 GND Ground
20
2 NC
No
Connection
19
3
LVDSA3
Diff. Data 3 (+)
18
4
LVDSA3#
Diff. Data 3 (–)
17
5 GND Ground
16
6
LVFSCLK0
Differential Clock (+)
15
7
LVDSCLK#
Differential Clock (–)
14
8 GND Ground
13
9
LVDSA2
Diff. Data 2 (+)
12
10
LVDSA2#
Diff. Data 2 (–)
11
11 GND
Ground
10
12
LVDSA1
Diff. Data 1 (+)
9
13
LVDSA1#
Diff. Data 1 (–)
8
14 GND
Ground
7
15
LVDSA0
Diff. Data 0 (+)
6
16
LVDSA0#
Diff. Data 0 (–)
5
17 GND
Ground
4
18 GND
Ground
3
19
+3.3V
Protected Power Supply
2
20
+3.3v
Protected Power Supply
1
