Multi-purpose I/O
VL-EPU-4562/4462 Reference Manual
38
User I/O Connector
The 40-pin user I/O connector incorporates the signals for the following:
Four USB ports
Eight GPIO lines (these are functionally muxed with six timer I/O signals per FPGA
registers). There are eight timer signals and they share digital I/Os 16-9. The eight GPIO
lines on the paddleboard each have an alternate mode, accessible using the FPGA’s
AUXMODE1 register. Refer to the
EPU-4562/4462 Programmer’s Reference Manual
for
more information on FPGA registers.
Three LEDs (two Ethernet link status LEDs and a programmable LED)
Two I
2
C signals (clock and data)
Push-button power switch
Push-button reset switch
Speaker output
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
The following figure shows the location and pin orientation of the user I/O connector.
Figure 16. Location and Pin Orientation of the User I/O Connector