6 Data Interface
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6.1.1
Trigger (Reset) Input (CC1)
This signal can be used to sync the acquisition of multiple cameras or to external events. Please see
chapter 5.4 for details.
6.1.2
Timing (FVAL, LVAL, DVAL, PCLK)
The Camera Link specification provides three synchronization signals:
•
FVAL (Frame Valid) – HIGH during transmission of valid lines of an image.
•
LVAL (Line Valid) – HIGH during transmission of valid pixels of a line.
•
DVAL (Data Valid) – HIGH in case that valid pixel data are present.
The gross pixel rate at the microbolometer sensor of the IRC-320 camera series is 5.25 MHz.
However, the maximum available bandwidth of the “Camera Link Base” configuration is not nearly
exploited; on the contrary, the transmission components require a minimum clock frequency for a safe
operation. For this reason the internal clock frequency is artificially increased by factor four before
being output as “Camera Link” clock signal. As a consequence an unnecessary high data rate would
occur at the grabber, why a multiple of the really needed data volume ought to be moved within the
storage of the receiver. Now the DVAL signal offers the opportunity to explicitly mark particular data
words as valid so that only the really needed pixel data is stored in the grabber’s memory.
For this reason attention has to be paid to the fact that when selecting a grabber and developing
software, the grabber does not only evaluate the signals FVAL and LVAL but also supports DVAL.
The following charts try to illustrate these facts:
DVAL
1 pixel (190 ns / 5.25 MHz)
PCLK
1 Camera Link clock (47.6 ns / 21 MHz)
DVAL
LVAL
320 pixels (60.95 µs)
Blanking
100 Pixels
(19.05 µs)
420 pixels (80 µs)
LVAL
FVAL
312 lines (24.96 ms)
s)
Blanking
ines
72 l
(5.76 ms)
240 lines (19.2 m
VDS Vosskühler GmbH
IRC-320
