Variscite VAR-320SBC, Reference Manual

Page: 34 / 42

VAR-320SBC Reference Guide
Copyright © 2008 Variscite
34
6.2. P2
Pin
num
Signal
Type
Description GPIO
1 L_PCLK O LCD Pixel clock 16_2
2 GND n/a
3 L_FCLK O LCD Frame clock 14_2
4 PWM_0
O
Pulse-width modulation output signal 11
5 L_LCLK O LCD Line clock 15_2
6
N.C.
n/a
7 V_BATT n/a
8
N.C.
n/a
9 L_BIAS O LCD AC bias/Data enable 17_2
10
N.C.
n/a
11 L_DD_0 O LCD Data line 6_2
12
N.C.
n/a
13 L_DD_1 O LCD Data line 7_2
14 GND n/a
15 L_DD_2 O LCD Data line 8_2
16 L_DD_16
O
LCD Data line 71
17 L_DD_3 O LCD Data line 9_2
18 L_DD_17
O
LCD Data line 72
19 V_BATT n/a
20 RESET_IN_N
I
Master reset input.
21 L_DD_4 O LCD Data line 10_2
22 nONKEY
I
On switch. Activates the National PMIC. n/a
23 L_DD_5 O LCD Data line 11_2
24
N.C.
n/a
25 L_DD_6 O LCD Data line 12_2
26 GND n/a
27 L_DD_7 O LCD Data line 13_2
28 ADC_IN1 A / D line input 1 n/a
29 L_DD_8 O LCD Data line 63
30 ADC_IN2 A / D line input 2 n/a
31 V_BATT n/a
32 CODEC_LINEOUTL Codec audio line out L n/a
33 L_DD_9 O LCD Data line 64
34 CODEC_LINEOUTR
I
Codec audio line out R
35 L_DD_10 O LCD Data line 65
36 N.C. n/a
37 L_DD_11 O LCD Data line 66
38 GND n/a
39 L_DD_12 O LCD Data line 67
40 EXT_WAKEUP1 I Wake-up signal to the PXA320.
41 L_DD_13 O LCD Data line 68