Vaisala RVP900, User Manual

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Appendix C. RVP900
Developer Notes
C.1 Customizing RVP Software
Vaisala provides a software environment to third-party developers wishing to customize
RVP algorithms.
This information only applies to organizations who have signed the Vaisala Software
Developer’s License Agreement.
This information is not relevant to the operational and scientific needs of most operators
and users.
RVP is an open-architecture radar signal processor that uses Gigabit Ethernet to interface to
the IFDR, which samples the data.
Using public APIs, researchers and OEM manufacturers can modify or replace existing
algorithms, or write their own software using the RVP900 software as a foundation.
RVP software runs under standard CentOS Linux, and is developed and maintained using
standard GNU tools (for example,
gcc
,
gdb
,
make
).
More Information
‣
Public API (page 40)
C.2 RVP Code Organization
RVP internal APIs provide abstraction from the underlying hardware. This means developers
do not need to worry about kernel support, interrupts, resource allocation, timing details,
and the interfaces to higher layers such as IRIS and its utilities.
Table 112 RVP Hardware and Software Organization
Component Description
PCI board Firmware The code that runs within the Field Programmable Gate Array (FPGA) chips on the PCI
cards.
The FPGA code is fundamental to the overall software model. All of the RVP real-time
functions are implemented at the chip level on one or more PCI cards.
This allows the remainder of RVP to run under standard (non real-time) Linux, because
no Linux process ever needs to respond to events with critically short latency. As long as
there is enough average CPU time during any 500 ms interval, all of the jobs get done
with no loss of data.
Appendix C – RVP900 Developer Notes
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