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Vaisala MPU112 Technical Reference Download Page 29

Chapter 9 _________________________________________________ Diagrams and Board Layouts

VAISALA _______________________________________________________________________ 27

CHAPTER 9

DIAGRAMS AND BOARD LAYOUTS

This chapter contains the technical drawings.

Main Processor MPU112

Table 4

MPU112 Technical Drawings

Code Description

DRW224327 Block

Diagram

DRW224328 Circuit

Diagram

DRW224343 Components

Layout

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Summary of Contents for MPU112

Page 1: ...TECHNICAL REFERENCE Main Processor Unit MPU112 M210829EN A ...

Page 2: ...mechanical including photocopying nor may its contents be communicated to a third party without prior written permission of the copyright holder The contents are subject to change without prior notice Please observe that this manual does not create any legally binding obligations for Vaisala towards the customer or end user All legally binding commitments and agreements are included exclusively in...

Page 3: ... 2 PRODUCT OVERVIEW 7 Introduction to MPU112 Main Processor Unit 7 CHAPTER 3 FUNCTIONAL DESCRIPTION 9 PC Core module 9 Flash Disk 10 CHAPTER 4 SYSTEM LOGIC PLD 11 Programmable Logic Device PLD 11 ISA Bus Interface 12 Address Decoders 12 Serial Channels 3 and 4 13 Interrupt Line Selectors 13 ARCNET Filter 13 Data Output Registers 13 Device Registers and Slot Rack Codes 13 CHAPTER 5 EXTERNAL COMMUNI...

Page 4: ... 20 Test Input 20 LED Lamp 20 CHAPTER 7 TEST PROGRAM 21 Test Program Overview 21 CHAPTER 8 TECHNICAL DATA 23 Control Processor 23 General 24 Connector Signal Layout 25 CHAPTER 9 DIAGRAMS AND BOARD LAYOUTS 27 Main Processor MPU112 27 CHAPTER 10 PARTS LIST 37 APPENDIX A CONNECTOR SIGNAL LIST 41 APPENDIX B FRONT PANEL CONNECTORS 45 COM1 Connector 45 ETH1 and ETH2 Connectors 45 APPENDIX C LIST OF SIGN...

Page 5: ... the product Chapter 2 Product Overview explains the operation and basic structure of the Vaisala Main Processor Unit MPU112 Chapter 3 Functional Description describes the functionality of the product Chapter 4 System Logic PLD provides information about the Programmable Logic Devices of the MPU112 Chapter 5 External Communication Interfaces provides information about the Ethernet and ARCNET local...

Page 6: ...d suggestions on the quality and usefulness of this publication If you find errors or have other suggestions for improvement please indicate the chapter section and page number You can send comments to us by e mail manuals vaisala com Safety General Safety Considerations Throughout the manual important safety considerations are highlighted as follows WARNING Warning alerts you to a serious hazard ...

Page 7: ...uipment housing To make sure you are not delivering high static voltages yourself Handle ESD sensitive components on a properly grounded and protected ESD workbench When this is not possible ground yourself to the equipment chassis before touching the boards Ground yourself with a wrist strap and a resistive connection cord When neither of the above is possible touch a conductive part of the equip...

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Page 9: ...aces from which the COM1 and COM2 communication ports are used in MPU112 The Carrier Board contains an Ethernet communication interface a Compact Flash type disk memory a Programmable Logic Device PLD two serial communication channels in addition to COM1 and COM2 ARCNET type local area network and a battery for the calendar clock of the CPU The Ethernet communication interface consists of an Ether...

Page 10: ...______________________________________________ M210829EN A Serial communication channels COM1 4 are used for external communication The COM1 2 channels are from Computer module and COM3 4 channels are from PLD logic ARCNET type local area network is used for the connection to other sounding system units ...

Page 11: ...dule It contains the following main parts CPU SDRAM controller and memory PCI bus interface ISA bus interface IDE bus interface Serial channels COM1 and COM2 CPU is a Pentium III processor The SDRAM memory is a 512 MB DDR SODIMM The PCI bus is used to connect to the10 100 Mbps Ethernet controller The ISA bus is used for a flash type BIOS memory and system logic PLD connections The IDE bus connects...

Page 12: ...e correct operation of the main system components Then it transfers the further code execution to the SDRAM system memory After BIOS is complete the processor boots from ATA flash disk memory loads code to PLD Programmable Logic Device and starts the execution of the actual application program Flash Disk The ATA IDE compatible flash disk is a Compact Flash CF type memory card It has a built in int...

Page 13: ...tains the power up code for D14 At power up the initial D14 code is automatically loaded from the code memory D16 Later in the system power up the final code is loaded from the system disk memory by the CPU processor The codes for D16 and D17 are loaded during unit manufacturing phase via the JTAG chain connection with the signals JTCK JTMS JTDI CMDO and JTDO The signal CMDO is the data output fro...

Page 14: ...art the configuration The PLD code is loaded in byte serial format using control signals PLDCS IOWR IORD and data bus PLDD0CONF data bit 0 SD01 SD07 data bit 7 The D14 output CONFD goes to high level to indicate properly completed configuration cycle The signal PLDD0CONF is used for data bit 0 only during configuration Later in the operation the signal SD00 is used as data 0 The resistors R64 R65 ...

Page 15: ...connections from device interrupts to CPU interrupt request lines ARCNET Filter A digital data filter for the incoming serial ARCNET data signal is provided See chapter ARCNET Interface for additional information Data Output Registers Control signals for the LED lamp and general purpose I O lines are provided Device Registers and Slot Rack Codes The PLD D14 contains a register for the device code ...

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Page 17: ...glueless PCI host interface Fully Integrated 10 100 Mbps Physical Layer Interface PHY Dual speed CSMA CD 10 Mbps and 100 Mbps Media Access Controller MAC compliant with IEEE ANSI 802 3 and Blue Book Ethernet standards Large independent internal TX and RX FIFOs EEPROM interface supports jumperless design and provides through chip programming Extensive programmable internal external loopback capabil...

Page 18: ... is for port 1 to 4 connections and part D5 C is for power connections Ports 1 and 2 are for external connections that are connected through transformers T1 and T2 to the front panel connectors ETH1 and ETH2 Ports 3 and 4 are connected via transformers to the system connector for internal use Port 5 is connected to the Ethernet controller The operation of each port is identical and includes the fo...

Page 19: ...ta packed along with its destination node number into the RAM buffer of the Controller and by issuing a command to enable the transmitter First the Controller waits for a token then it sends an enquiry to the destination node If the node is free to receive it responds with an acknowledgment and the Controller performs the transmit sequence If the transmit sequence is completed successfully the rec...

Page 20: ...riven to the line by the transmitter The enable and data signals ARCTXEN and ARCTX are connected to the transmitter via PLD D14 Serial Channels The MPU112 has four serial channels for external serial communication All channels have RS232 compatible line drivers and receivers Channels 1 and 2 are provided by the Computer Module Both channels are supported by the internal baud rate generators Channe...

Page 21: ...operating voltage falls below 3 0 V 2 5 V operating voltage falls below 2 2 V optional internal reset line SELFRES is in 0 state external reset line MRES is in 0 state The reset output signals are held active typically 200 ms after the reset condition has disappeared PLL Clock Multipliers PLL Phase Locked Loop clock multiplier D8 is programmed to generate 20 MHz output from 25 MHz input clock The ...

Page 22: ...e PLD The input is for future testing purposes it is not used in normal operation LED Lamp The Status lamp V1 is a red green bi color LED type lamp The red and green lamps are controlled by signals REDLED and GRNLED from the PLD D14 Yellow color is produced when both lamps are on During system reset yellow color is shown After reset yellow lamp remains on during the boot sequence of the Computer M...

Page 23: ...e verifies the correct operation of the following system components CPU ISA bus and BIOS code flash PCI bus and connection to Ethernet controller SDRAM system memory If a fault is detected the operation is halted and the yellow LED remains on to indicate the faulty unit In correct operation the further BIOS code execution is transferred to the SDRAM system memory After the BIOS is complete the pro...

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Page 25: ...chapter contains the MPU112 technical specifications Control Processor Table 1 Technical Data for Control Processor Part Specification PC Module Processor type AMD Geode LX800 Clock rate 500 MHz Memory DDR SODIMM 512 MB 2nd Level Cache 128 kB Flash disk ATA IDE CF card 1 GB Communication channels Ethernet port 10 100 Mbps two switch ports Serial lines RS232C four channels Local Area Network ARCNET...

Page 26: ...ification Power requirements 3 3 V 5 700 mA 5 V 5 1600 mA Operating conditions Temperature 0 55ºC standard 30 55ºC extended Humidity Non condensing Storage conditions Temperature 55 80ºC Humidity Non condensing Dimensions and mass Unit type E1 size printed circuit board Length width height 190 x 128 x 30 5 mm Weight 520 g System connector Connector type 220 pin female LED Lamp Status indicator Bi ...

Page 27: ...I O HD0 I O 10 HD15 I O HDRQ O HDWR O HDRD O HDRDY I 11 HDACK O HDIRQ I HDIOC16 I O HDA1 O PDIAG I O 12 HDA0 O HDA2 O HCS0 O HCS1 O DASP I O 13 14 15 16 17 18 ARC I O ARC I O 19 TXD6 O 20 RXD6 I 21 TXD5 O 22 RXD5 I 23 GND GND GND GND GND 24 E3RX I E3RX I GND E3TX O E3TX O 25 GND GND GND GND GND 26 E4RX I E4RX I GND E4TX O E4TX O 27 GND GND GND GND GND 28 TXD3A O TXD3B O TXD3C O TXD3C O 29 RXD3A I ...

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Page 29: ...__________________________________________________________________ 27 CHAPTER 9 DIAGRAMS AND BOARD LAYOUTS This chapter contains the technical drawings Main Processor MPU112 Table 4 MPU112 Technical Drawings Code Description DRW224327 Block Diagram DRW224328 Circuit Diagram DRW224343 Components Layout ...

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Page 31: ...Chapter 9 _________________________________________________ Diagrams and Board Layouts VAISALA _______________________________________________________________________ 29 ...

Page 32: ...TECHNICAL REFERENCE___________________________________________________________ 30 __________________________________________________________________ M210829EN A ...

Page 33: ...Chapter 9 _________________________________________________ Diagrams and Board Layouts VAISALA _______________________________________________________________________ 31 ...

Page 34: ...TECHNICAL REFERENCE___________________________________________________________ 32 __________________________________________________________________ M210829EN A ...

Page 35: ...Chapter 9 _________________________________________________ Diagrams and Board Layouts VAISALA _______________________________________________________________________ 33 ...

Page 36: ...TECHNICAL REFERENCE___________________________________________________________ 34 __________________________________________________________________ M210829EN A ...

Page 37: ...Chapter 9 _________________________________________________ Diagrams and Board Layouts VAISALA _______________________________________________________________________ 35 ...

Page 38: ...TECHNICAL REFERENCE___________________________________________________________ 36 __________________________________________________________________ M210829EN A ...

Page 39: ...er SMDSMTU2430 1 1 Assembly ref 008 218932 IC Compact Flash Card SSD C01GI 3512 1 Assembly ref 009 DRW213186 Bracket 4x6x12 1 Assembly ref 010 219019 License Sticker EMBOS Win XP Full Run UK 1 Assembly ref 011 15224 STICKER 20x8mm 4x1000 reel Software version Label Will be installed in Vaisala 1 Assembly ref 012 15223 Sticker Set Matt White Polyethylene serial number and barcode 1 Assembly ref 013...

Page 40: ...20 23 27 35 37 44 46 53 55 60 64 65 67 69 74 75 77 79 82 96 100 102 111 112 117 118 121 124 131 134 137 141 151 26100 Resistor Chip 100R 1 0 100ppm 0603 70 R5 R7 R9 R10 R13 R127 130 R152 26097 Resistor Chip 0R0 jumper 0603 10 R8 11 16 22 25 26 36 73 78 81 83 85 95 97 99 101 103 104 116 125 135 138 140 142 146 148 150 25262 Resistor Chip 10K0 1 0 100ppm 0603 37 R12 21 45 54 63 66 71 7 2 76 80 84 10...

Page 41: ...2C1H9L 2 Z2 210863 Oscillator Crystal 25 000 MHz SMD 1 Miscellaneous 4613 0 Wire Hook Up PTFEAWG26 0 16mm Black for X4 wiring H1 1 4613 1 Wire Hook Up PTFEAWG26 0 16mm Brown for X4 wiring H2 1 4613 2 Wire Hook Up PTFE ExAWG26 0 16mm Red for X4 wiring H3 1 211738 Screw Crosshead M2 5x6 DIN7985 PZ A4 2 212419 Screw Crosshead M2x6 DIN7985 PZ A4 4 212420 Screw Crosshead M2x12 DIN7985 PZ A4 2 213797 Sc...

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Page 43: ...ynch 5 V a5 VGAVX VGA Vertical Synch 5 V b5 KBDATA Keyboard Data 5 V c5 KBCLK Keyboard Clock 5 V d5 MSDATA Mouse Data 5 V e5 MSCLK Mouse Clock 5 V a b6 USBCLK DATA USB Universal Serial Bus USB differential line USB e6 RESDRV HD Hard Disk Reset 3 3 V a7 a10 HD0 15 HD Data Bus 5 V b10 HDRQ HD Data Request 5 V c10 HDWR HD Write 5 V d10 HDRD HD Read 5 V e10 HDRDY HD Data Ready 3 3 V a11 HDACK HD Data ...

Page 44: ...nel 3C differential line RS422 a30 TxD2 Data output for serial channel 2 RS232 b30 DTR2 Data Terminal Ready for serial channel 2 RS232 c30 RTS2 Ready to Send for serial channel 2 RS232 a31 RxD2 Data input for serial channel 2 RS232 b31 DSR2 Data Set Ready for serial channel 2 RS232 c31 CTS2 Clear to Send for serial channel 2 RS232 a32 TxD1 Data output for serial channel 1 RS232 b32 TxD4 Data outpu...

Page 45: ...Level a e44 5 V 5 V operating voltage a45 FINDEXR0 Floppy Disk Index Rack0 for Arcnet address 5 V b45 FTRK0R1 Floppy Disk Track Zero Rack1 for Arcnet address 5 V c45 FWRPRTR2 Floppy Disk Write Protected Rack2 for Arcnet address 5 V d45 FRDATAR3 Floppy Disk Read Data Rack3 for Arcnet address 5 V e45 FDCHGR4 Floppy Disk Change Rack4 for Arcnet address 5 V NOTE Signal marked by are 0 level active ...

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Page 47: ... Signal List and Layout Signal Pin Description Level RxD1 2 Data input for serial channel RS232C TxD1 3 Data output for serial channel RS232C GND 5 Ground ETH1 and ETH2 Connectors Two Ethernet channels 10 100 Mbit s Type of connector RJ45 female Corresponding cable connector RJ45 male Table 2 ETH1 and ETH2 Connectors Signal List and Layout Signal Pin Description Level ETX 1 Data output for Etherne...

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Page 49: ...T Battery voltage VSTBY Standby voltage 20MHZ 20 MHz clock signal 25MHZ 25 MHz clock signal AEN Address enable AGND Analog ground ALE Address latch enable ARC Non inverted ARCNET line ARC Inverted ARCNET line ARCRXIN Received ARCNET data ARCRXINP Received ARCNET data ARCTX Transmitted ARCNET data ARCTXEN ARCNET transmitter enable ARCTXENP ARCNET transmitter enable ARCTXP Transmitted ARCNET data CM...

Page 50: ...ction from resistor FDR0 Floppy disk drive 0 FDR0R Floppy disk drive 0 from resistor FHDSEL Floppy disk head select FHDSELR Floppy disk head select from resistor FINDEXR0 Floppy disk index FMTR0 Floppy disk motor 0 FMTR0R Floppy disk motor 0 from resistor FRAME PCI frame FRDATAR3 Floppy disk read data FSTEP Floppy disk step FSTEPR Floppy disk step from resistor FTRK0R1 Floppy disk track 0 FWDATA F...

Page 51: ...rom buffer IPX1 2 Input 1 2 IRDY PCI initiator ready IRQ1 15 Interrupt request 1 15 ISA Industry standard architecture JTAG Joint testability action group JTCK JTAG test clock in JTCKIN JTAG test clock input JTDI JTAG test data in JTDIN JTAG test data input JTDO JTAG test data out JTDOUT JTAG test data output JTDOUTR JTAG test data output from resistor JTMS JTAG test mode select JTMSIN JTAG test m...

Page 52: ...odule PERR Parity error PINT Peripheral interrupt PLD Programmable logic device PLDCONFD PLD config done PLDCONFIG PLD config PLDCONFIGR PLD config from resistor PLDCS PLD chip select PLDD0CONF PLD data 0 config PLDD0CONFR PLD data 0 config from resistor PLDDCLK PLD data clock PLDDCLKR PLD data clock from resistor PLDMSEL0 1 PLD mode select 0 1 PLDSTATUS PLD status PLDSTATUSR PLD status from resis...

Page 53: ...input TRDY PCI target ready TXD1 6 Transmitted serial data 1 6 TXD3A Transmitted serial data 3A TXD3B Transmitted serial data 3B TXD3C TXD3C Transmitted serial signal pair 3C TS1 5 Test signal 1 5 TSR1 5 Test signal 1 5 from Computer Module UART Universal asynchronous receiver transmitter USB Universal serial bus USBCLK USB clock USBCLKR USB clock from resistor USBDATA USB data USBDATAR USB data f...

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